Senior SRAM Circuit Design Engineer

The Digital IP (DIP) group at NVIDIA is seeking a skilled and creative SRAM circuit designer for a high-visibility position. This role involves:

1. Embedded SRAM design: Transistor-level circuit design, supervising layout implementation, physical and logical verification, and debug of SRAM macros.

2. SRAM compiler development: Envisioning, defining, and coding efficient ways to automate the assembly and validation of multiple unique SRAM macros using NVIDIA's extensive compute resources.

3. Advanced development: Exploring future process nodes and developing techniques for optimal power, performance, and area characteristics.

4. Collaboration: Working with SOC design partners, silicon test teams, and productization teams to achieve performance goals, guide testing efforts, and prepare new silicon for real-world applications.

The ideal candidate will have:

• BSEE minimum (MSEE or PhD preferred)
• 5+ years of SRAM design experience on advanced FinFET processes
• Experience with single-port, dual-port, or register file SRAM-based macros
• Python scripting ability
• Successful track record of delivering designs to production

Additional desirable skills:

• Self-motivation and attention to detail
• Strong communication and presentation skills
• Advanced Python scripting expertise
• Familiarity with Cadence schematic and layout capture tools
• Silicon testing/debug experience

NVIDIA, known for inventing the GPU and revolutionizing parallel computing, continues to evolve and adapt to new challenges. Join our diverse team and be part of our mission to amplify human imagination and intelligence through technological innovation.