Senior Timing and Constraints Methodology Engineer
Description For Senior Timing and Constraints Methodology Engineer
NVIDIA, a pioneer in GPU technology and AI computing, is seeking a Senior Timing and Constraints Methodology Engineer to join their innovative team. This role is crucial for developing cutting-edge timing sign-off strategies for next-generation GPUs and SoCs, working with deep sub-micron design (3nm and beyond). The position combines hardware engineering expertise with software development, requiring strong skills in both domains.
The role involves developing and implementing sophisticated methodologies for timing constraint validation, working with industry-standard tools like PrimeTime and SNPS TCM. You'll be responsible for creating scalable, reusable STA environments and ensuring timing accuracy across complex hierarchical designs. This position requires expertise in RTL clock constructs, constraint validation, and automation using languages like Python and C++.
NVIDIA offers a competitive compensation package, including a base salary range of $168,000 - $310,500, plus equity and comprehensive benefits. The company is known for its cutting-edge work in AI computing and is consistently ranked as one of the technology world's most desirable employers. This role provides an opportunity to work on some of the most complex and challenging problems in semiconductor design, directly contributing to the future of computing technology.
The ideal candidate will have an MS in Electrical or Computer Engineering with 4+ years of experience in ASIC Design and Timing, along with expertise in various technical tools and methodologies. You'll be joining a collaborative environment where innovation and technical excellence are highly valued, working alongside some of the industry's best minds in hardware design and engineering.
Responsibilities For Senior Timing and Constraints Methodology Engineer
- Develop methodologies and flows to validate constraints with industry-standard tools
- Support tapeout-quality STA environments that are scalable and reusable
- Analyze RTL clock constructs to derive clock definitions
- Interpret hierarchical clock structures
- Write automation scripts in Perl, Python, and C++
- Create and enforce clock-related structural checks
- Collaborate with RTL, physical design, and verification teams
Requirements For Senior Timing and Constraints Methodology Engineer
- MS (or equivalent experience) in Electrical or Computer Engineering with 4+ years' experience in ASIC Design and Timing
- Expertise in Primetime and timing constraints
- Knowledge of device physics, STA methodology
- Exposure to RTL to GDSII flows
- Good understanding of mathematics/physics fundamentals of electrical design
- Expertise in coding- TCL, Python, C++
- Strong communications skill and good standout colleague
Benefits For Senior Timing and Constraints Methodology Engineer
- Equity
- Medical Benefits
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