STA Engineer

NVIDIA is seeking exceptional STA (Static Timing Analysis) Physical Design Engineers to join their Networking DFT team. This role focuses on developing industry-leading high-speed communication devices that deliver maximum throughput and minimal latency. As an STA Engineer, you'll be integral to designing groundbreaking chips in a professional, growth-oriented environment.

The position involves sophisticated timing analysis work, including RTL constraints management, DFT timing verification, and full chip-level analysis. You'll collaborate with expert teams handling both pre and post-silicon aspects, working on challenging designs that require deep silicon implementation understanding. The role demands strong technical expertise in physical design flows and methodologies, with opportunities to work with cutting-edge EDA tools from industry leaders like Synopsys and Cadence.

NVIDIA offers an environment where you can make significant contributions to technology advancement. The company's leadership in accelerated computing, AI, and digital twins makes it an exciting workplace for engineers passionate about pushing technological boundaries. You'll be part of a team developing solutions that transform major industries and impact society meaningfully.

The ideal candidate combines technical expertise with strong communication skills and teamwork abilities. While the core requirements include a B.Sc. in Electrical/Computer Engineering and 2-3 years of STA experience, knowledge of DFT flows, CDC, and physical design tools would be particularly valuable. This role presents an excellent opportunity for growth and impact in one of technology's most innovative companies.