ASIC RTL Design (Turing) - Engineer

Qualcomm is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all.
Backend
Mid-Level Software Engineer
In-Person
6+ years of experience
AI
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Description For ASIC RTL Design (Turing) - Engineer

Qualcomm is seeking an ASIC RTL Design Engineer for their Turing team in Noida, India. This role requires 6-12 years of experience in hardware engineering or related fields. The ideal candidate will work closely with product definition and architecture teams to develop implementation strategies for subsystems, focusing on microarchitecture and coding to meet quality and PPAS (Performance Power Area Schedule) goals.

Key responsibilities include:

  • Defining block-level design aspects such as block diagrams, interfaces, clocking, transaction flow, pipeline, and low power solutions
  • Leading a team of engineers in RTL coding for subsystem/SOC integration and function/performance simulation debug
  • Driving Lint/CDC/FV/UPF checks to ensure design quality
  • Developing assertions for white-box testing coverage
  • Collaborating with stakeholders to discuss collateral quality and identify solutions/workarounds
  • Delivering key design collaterals (timing constraints, UPF, etc.)

Required skills and knowledge:

  • Strong understanding of low power microarchitecture techniques and AI/ML systems
  • Thorough knowledge of computer system architecture, including design aspects of AI/ML designs
  • Experience in high-performance design techniques and trade-offs in computer microarchitecture
  • Good understanding of NoC Design principles
  • Ability to define performance (bandwidth, latency) and bus transactions sizing based on use cases across voltage/frequency corners
  • Experience working with power and synthesis teams on use cases, dynamic power, and datapath interactions
  • Proficiency in Verilog / System Verilog, with experience using simulators and waveform debugging tools
  • Familiarity with SOC DFT and PD teams for collateral exchanges
  • Knowledge of logic design principles and their timing and power implications

Qualcomm offers a comprehensive benefits package, including health coverage for employees and eligible dependents, financial planning assistance, and programs to support emotional/mental strength and resilience. The company is committed to fostering a diverse and inclusive work environment that encourages innovation and breakthrough technologies.

Join Qualcomm to be part of a team that's shaping the future of technology and pushing the boundaries of what's possible in the world of AI and machine learning.

Last updated 7 months ago

Responsibilities For ASIC RTL Design (Turing) - Engineer

  • Interact closely with product definition and architecture teams
  • Develop implementation strategies for subsystems, focusing on microarchitecture and coding
  • Define block-level design aspects such as block diagrams, interfaces, clocking, transaction flow, pipeline, and low power solutions
  • Lead a team of engineers in RTL coding for subsystem/SOC integration and function/performance simulation debug
  • Drive Lint/CDC/FV/UPF checks to ensure design quality
  • Develop assertions for white-box testing coverage
  • Collaborate with stakeholders to discuss collateral quality and identify solutions/workarounds
  • Deliver key design collaterals (timing constraints, UPF, etc.)
  • Define performance (bandwidth, latency) and bus transactions sizing based on use cases across voltage/frequency corners
  • Work with power and synthesis teams on use cases, dynamic power, and datapath interactions
  • Collaborate with SOC DFT and PD teams for collateral exchanges

Requirements For ASIC RTL Design (Turing) - Engineer

  • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience
  • Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience
  • PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience
  • 6 to 12 years of experience in hardware engineering or related fields
  • Strong understanding of low power microarchitecture techniques and AI/ML systems
  • Thorough knowledge of computer system architecture, including design aspects of AI/ML designs
  • Experience in high-performance design techniques and trade-offs in computer microarchitecture
  • Good understanding of NoC Design principles
  • Proficiency in Verilog / System Verilog
  • Experience with simulators and waveform debugging tools
  • Knowledge of logic design principles and their timing and power implications

Benefits For ASIC RTL Design (Turing) - Engineer

Medical Insurance
401k
  • World-class health benefit coverage for employees and eligible dependents
  • Financial planning assistance programs
  • Emotional and mental strength support resources
  • Wellbeing programs to help employees Live+Well and Work+Well
  • Continuous learning and development programs
  • Tuition reimbursement
  • Mentorship opportunities

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