Qualcomm Technologies, Inc. is seeking an experienced ASICS Design Verification Engineer to join their innovative team in Santa Clara. This role represents an exciting opportunity to work with a leading technology innovator that consistently pushes the boundaries of what's possible in communication and data processing transformation.
The position involves comprehensive responsibility for the complete verification lifecycle of digital power IP's, from initial system-level concept through to tape out and post-silicon support. The successful candidate will be deeply involved in advanced verification methodologies, working with cutting-edge technologies and tools including SystemVerilog-UVM, coverage development, and formal verification.
Key responsibilities include developing pre-silicon test plans, creating sophisticated testbench environments, implementing assertion models, and deploying power-aware UPF verification flows. The role also emphasizes automation development to enhance verification efficiency, making it perfect for someone who combines technical expertise with innovative problem-solving skills.
The ideal candidate will bring at least 10 years of experience in ASIC design and verification, along with deep knowledge of digital design concepts and RTL languages. Strong programming skills in C/C++ and scripting capabilities in Perl or Python are essential. The position offers competitive compensation ranging from $176,300 to $264,500, complemented by an attractive benefits package including annual bonuses, RSU grants, and comprehensive health coverage.
This role presents an excellent opportunity for career growth within a dynamic team that's driving technological innovation. Working at Qualcomm means being part of a company that values continuous learning, professional development, and work-life balance. The position offers the chance to work on cutting-edge projects while collaborating with some of the industry's brightest minds in ASIC design and verification.