CPU STA/Timing Analysis Engineer (All Levels)
Description For CPU STA/Timing Analysis Engineer (All Levels)
Qualcomm, a leading technology innovator, is seeking a CPU STA/Timing Analysis Engineer to join their team in Bangalore. This role is part of Qualcomm's Hardware Engineering group, where you'll be responsible for crucial timing analysis and optimization of complex SOC designs. The position requires a deep understanding of hardware engineering principles and timing closure methodologies.
As a Physical Design Timing Engineer, you'll collaborate with cross-functional teams including microarchitecture, RTL design, CAD, and physical design teams. Your primary focus will be on running and analyzing timing, driving timing closure, and working with various teams to implement and validate constraints. The role demands expertise in industry-standard tools and deep submicron process technology.
The ideal candidate should possess an MS in Electrical Engineering with 10 years of practical experience, though candidates with different experience levels will be considered. You'll need strong technical skills in STA, timing flows, and multi-clock domain designs, combined with excellent communication abilities to work effectively across teams.
Qualcomm offers an exceptional work environment with comprehensive benefits, including world-class health coverage, financial planning programs, and continuous learning opportunities. The company's commitment to innovation and technological advancement makes this an exciting opportunity for someone looking to work on cutting-edge hardware engineering projects.
This role offers significant growth potential within a company that's at the forefront of technological innovation, particularly in mobile and wireless technologies. You'll be part of a team that pushes the boundaries of what's possible in hardware engineering while working on projects that have global impact.
Responsibilities For CPU STA/Timing Analysis Engineer (All Levels)
- Work with design and DFT teams to understand, implement and validate constraints
- Run SOC timing runs at all hierarchies
- Analyze timing and work with RTL/DFT teams to facilitate logic changes required
- Feedback to block level and top level physical design engineers on key fixes required for timing closure
- Work with CAD team to implement timing infrastructure
- Create ECOs from timing runs to help timing closure
- Document and help with timing methodology definition
Requirements For CPU STA/Timing Analysis Engineer (All Levels)
- MS degree in Electrical Engineering with 10 years of practical experience
- Experience in timing flows with industry standard tools
- Experience in all aspects of timing closure for multi-clock domain designs
- Experience in deep submicron process technology nodes
- Experience with STA on large SOC with multi-scenario timing closure
- Experience with Timing ECO techniques and implementation
- Knowledge of library cells and optimizations
- Familiar with circuit modeling, transistor fundamentals and worst case corner selection
- Solid understanding industry standard tools for synthesis, place & route and tapeout flows
- Good communication skills
- Knowledge of all aspects of timing including noise, cross-talk and others
- Knowledge of basic SoC architecture and HDL languages like Verilog
Benefits For CPU STA/Timing Analysis Engineer (All Levels)
- World-class health coverage for employees and eligible dependents
- Financial planning and future preparation programs
- Emotional/mental strength and resilience support
- Wellbeing programs
- Continuous learning and development programs
- Tuition reimbursement
- Mentorship programs
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