High-Speed PLL Digital Design Lead Engineer
Description For High-Speed PLL Digital Design Lead Engineer
Qualcomm India Private Limited is seeking a High-Speed PLL Digital Design Lead Engineer to join their Hardware Engineering team in Bangalore. This role focuses on front-end digital design implementation of high-speed PLL designs and requires extensive experience in RTL development, validation, and chip-level integration.
The position demands expertise in digital design implementation, with responsibilities spanning from RTL development and validation to SoC integration and chip-level debug. You'll be working on cutting-edge PLL designs, handling complex timing constraints, and ensuring optimal power performance through UPF implementation and power-aware checks.
The ideal candidate should have at least 5 years of hardware engineering experience, with a strong background in micro-architecture development and RTL design. A Bachelor's or Master's degree in Computer Science, Electrical/Electronics Engineering, or a related field is required. Experience with post-silicon bring-up and debug is considered a plus.
At Qualcomm, you'll be part of a global team working on innovative technologies that shape the future of wireless communication. The company offers comprehensive benefits and a collaborative work environment where you can grow your career alongside industry experts. You'll have opportunities to contribute to world-changing innovations while working with some of the brightest minds in the industry.
The role offers exposure to advanced hardware design techniques and tools, working with cross-functional teams across the globe. You'll be involved in all aspects of the design process, from initial implementation to final validation, making this an excellent opportunity for someone looking to take their hardware engineering career to the next level.
Responsibilities For High-Speed PLL Digital Design Lead Engineer
- Front-End/Digital design implementation of high speed PLL designs
- RTL development and its validation for linting, clock-domain crossing, conformal low power and DFT rules
- Work with functional verification team on test-plan development and debug
- Develop timing constraints, deliver synthesized netlist to physical design team
- UPF writing, power aware equivalence checks and low power checks
- DFT insertion and ATPG analysis for optimal SAF, TDF coverage
- Provide support to SoC integration and chip level pre/post-silicon debug
Requirements For High-Speed PLL Digital Design Lead Engineer
- Bachelor's/Master's degree in Computer Science, Electrical/Electronics Engineering or related field
- 5+ years of Hardware Engineering experience
- Experience in micro-architecture development, RTL design, front-end flows
- Experience with post-silicon bring-up and debug is a plus
- Able to work with teams across the globe and possess good communication skills
Benefits For High-Speed PLL Digital Design Lead Engineer
- World-class health coverage for employees and dependents
- Financial planning and future security programs
- Emotional/mental strength and resilience support
- Comprehensive wellbeing programs
- Continuous learning and development programs
- Tuition reimbursement
- Mentorship opportunities
