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LPASS DV Sr Engineer

Leading technology innovator that develops mobile computing and telecommunications products
Embedded
Senior Software Engineer
In-Person
5,000+ Employees
6+ years of experience
AI · Consumer
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Description For LPASS DV Sr Engineer

Qualcomm, a leading technology innovator, is seeking a Senior LPASS DV Engineer to join their Hardware team in Bangalore. This role is part of the worldwide team responsible for developing and delivering cutting-edge Audio solutions that set benchmarks in the mobile computing industry. As a Hardware Engineer at Qualcomm, you'll be involved in planning, designing, optimizing, verifying, and testing electronic systems, particularly focusing on the Low Power Audio Subsystem (LPASS).

The position requires deep understanding of hardware architecture while working with the latest DV tools and technologies. You'll be responsible for DV ownership of LPASS core features, developing robust testbenches, and exploring innovative verification methodologies across formal, simulation, and emulation approaches. The goal is to ensure bug-free silicon for Tape Out, ultimately contributing to superior user experiences on Snapdragon-based computing devices.

This role offers an exciting opportunity to work with Qualcomm's renowned audio solutions, including the Qualcomm Aqstic technology. You'll be collaborating with cross-functional teams to develop solutions and meet performance requirements, while pushing the boundaries of what's possible in mobile audio technology.

The ideal candidate should have strong expertise in HDLs like Verilog and System Verilog, proficiency in SV/UVM based test benches, and excellent debugging skills using tools like Verdi. Knowledge of UPF and low power architecture is preferred. This position offers the chance to work on next-generation experiences and help create a smarter, connected future while being part of a global leader in mobile technology innovation.

Last updated 20 days ago

Responsibilities For LPASS DV Sr Engineer

  • DV ownership of one or more features in the Low power audio subsystem(LPASS) core
  • Developing a robust testbench, optimized for the specific feature/DUT
  • Explore innovative DV methodologies (formal, simulation and emulation based)
  • Ensure a bug free silicon for Tape Out

Requirements For LPASS DV Sr Engineer

Linux
  • 1-6 years of VLSI industry experience
  • Strong debugging and analytical skills
  • Strong knowledge of HDLs like Verilog, System Verilog
  • Proficiency in developing SV/UVM based test benches
  • Proficient in debugging RTL/TB issues using Verdi or similar tools
  • Proficient with scripting languages such as Perl and(or) Python
  • Knowledge of UPF, low power architecture

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