NoC Interconnect Design Engineer and Architect
Description For NoC Interconnect Design Engineer and Architect
Qualcomm Technologies, Inc. is seeking a NoC Interconnect Design Engineer and Architect to join their team in San Diego. This role is part of the NoC bus team, a multi-disciplinary group involved in early product specification through final RTL delivery to SoCs. The position requires expertise in bus protocols, synthesis tools, and VLSI design, with a focus on creating micro-architecture specifications and analyzing performance results.
The ideal candidate will have strong knowledge of ASIC flow and bus protocols, with the ability to identify architecture bottlenecks and drive micro-architecture choices. You'll be responsible for evaluating new IPs, delivering RTL, and supporting verification teams. The role offers competitive compensation ranging from $140,000 to $210,000, plus comprehensive benefits including annual bonuses and RSU grants.
Qualcomm provides an innovative environment where you'll work alongside leading engineering experts, with opportunities for continuous learning and professional growth. The company offers extensive benefits covering health, wealth, and wellbeing, including medical coverage, 401k, and mental health support. This position is perfect for experienced engineers passionate about hardware design and ready to contribute to cutting-edge technology development at a global leader in wireless innovation.
Responsibilities For NoC Interconnect Design Engineer and Architect
- Creating micro-architecture bus components specifications
- Analyzing performance results
- Delivering RTL and running tool flows
- Evaluating new IPs
- Driving new protocol deployments
- Defining system wide guidelines for IPs
- Supporting verification and silicon validation teams
- Working with SW teams for successful deployments of interconnects
Requirements For NoC Interconnect Design Engineer and Architect
- Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design experience
- Knowledge of various bus protocols (AHB, AXI, CHI)
- Strong working knowledge of architecture tradeoff analysis
- Strong knowledge of ASIC flow (synthesis, STA, Lint), power tools
- Skills for trouble shooting and problem solving
- RTL design, FPGA and post-silicon debug experience
- Excellent communication skills
Benefits For NoC Interconnect Design Engineer and Architect
- Competitive annual discretionary bonus program
- Annual RSU grants
- Comprehensive health coverage
- Financial planning assistance
- Mental health and wellbeing support
- Continuous learning and development programs
- Tuition reimbursement
- Mentorship programs
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