PMIC Lead Layout Engineer

Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues.

Key Responsibilities: • Extensive floor planning and signal planning skills in Cadence Virtuoso IC201 and above. • Layout Design for various analog circuits like Linear and Switching Regulators, ADCs, DACs, CHARGERS, Envelope Trackers, APTs, High Current POWERFETS, OTAs, Error Amplifiers etc. • Strong understanding of submicron, deep-submicron, High Voltage CMOS processes. • Very strong analog layout fundamentals and basic electrical knowledge for layout development. • Strong physical verification debugging capability using Calibre Verification Suite. • Create area and parasitic efficient layouts, with strong problem-solving skills. • Ability to perform in a dynamic, team-oriented environment. • Well-developed organizational skills and the ability to multi-task. • Strong communication skills for efficient delivery. • Team player skills to work with geographically spread team members. • Create technical documentation and presentations.

Requirements: • Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 2+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. • OR Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 4+ years of experience designing custom layouts in relevant domain. • OR High School diploma or equivalent and 6+ years of experience designing custom layouts in relevant domain. • 2+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap). • Graduation in Electrical or Electronics is preferred with 4+ years of exp. • Diploma with minimum 7 years of hands-on layout development experience.

Additional Skills: • SOI process knowledge is an advantage. • Scripting knowledge in SKILL/PERL/SHELL is an advantage.

Qualcomm is an equal opportunity employer and is committed to providing reasonable accommodations to individuals with disabilities during the application/hiring process.