SOC Design Verification Staff Engineer - Hyd
Description For SOC Design Verification Staff Engineer - Hyd
Qualcomm is seeking a Staff-level SOC Design Verification Engineer to join their team in Hyderabad. This role focuses on verification of highly complex automotive, compute, mobile, XR-VR, and IoT SOCs. The position requires deep expertise in digital ASIC verification and system-level hardware understanding.
As a DV Engineer, you'll be responsible for architecting verification strategies, developing test plans, and ensuring designs meet the highest quality standards. The role involves early participation in product architecture definition and working throughout the complete verification lifecycle. You'll work with cutting-edge technologies across multiple domains including automotive, AR/VR, and AI applications.
The ideal candidate brings 5+ years of verification experience with strong skills in System Verilog/UVM and comprehensive understanding of low power design techniques. You'll be working with a team of experts in hardware engineering, contributing to Qualcomm's innovation in wireless technology and semiconductor development.
Qualcomm offers an exceptional benefits package including comprehensive health coverage, financial planning support, and continuous learning opportunities. The company fosters a culture of innovation where employees can contribute to world-changing technologies while developing their careers alongside industry experts.
This role provides an opportunity to work on next-generation SOC designs while being part of a global technology leader. You'll have access to mentorship programs, tuition reimbursement, and various professional development opportunities. The position offers the chance to work on complex technical challenges while contributing to products that impact millions of users worldwide.
Responsibilities For SOC Design Verification Staff Engineer - Hyd
- Define verification architecture, develop test plans and build verification environment
- Work with design team to understand design intent
- Verify Subsystems and Full SoC using advanced verification methodologies
- Build agents and checkers from scratch
- Develop test plan to verify all low power aspects
- Own end to end DV tasks
- Assist in silicon bring-up, debug and bring-up activities
Requirements For SOC Design Verification Staff Engineer - Hyd
- B.E/B.Tech/M.E/M.Tech in Electronics with 5+ year experience in verification domain
- Strong fundamentals in digital ASIC verification
- Experience in IP/SS/SoC level verification
- System Verilog/UVM based verification skills
- Working knowledge of Interconnect architecture and Bus protocols
- Good understanding of low power design techniques
- Experience with UPF/CPF based power aware verification
- Knowledge of Multimedia design blocks
- Knowledge of peripheral blocks verification
Benefits For SOC Design Verification Staff Engineer - Hyd
- World-class health coverage for employees and dependents
- Financial planning and future preparation programs
- Emotional/mental strength and resilience support
- Wellbeing programs
- Continuous learning and development programs
- Tuition reimbursement
- Mentorship programs
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