Network Packet Processing Core DV Sr Engineer
Description For Network Packet Processing Core DV Sr Engineer
Qualcomm, a global leader in technology innovation, is seeking a Senior Network Packet Processing Core DV Engineer to join their team in Bangalore, India. This role sits at the intersection of hardware engineering and digital verification, requiring 2-5 years of experience in digital front-end ASIC design verification.
The position offers an opportunity to work on next-generation complex cores used in High-End Modem/Mobile chips. The successful candidate will be responsible for developing verification environments, implementing test cases, and ensuring comprehensive coverage of design features. Key responsibilities include developing testbench components, performing RTL code coverage, and conducting verification reviews.
This role requires expertise in System Verilog and UVM-based verification, along with a strong understanding of bus protocols and TCP/IP Packet Processing Algorithms. The ideal candidate should have a Bachelor's or Master's degree in Electronics, VLSI, Communications, or a related field.
Qualcomm offers a comprehensive benefits package including world-class health coverage, financial planning programs, and wellbeing resources. The company is committed to fostering a supportive, inclusive culture where innovative ideas can flourish. Employees have access to continuous learning opportunities, tuition reimbursement, and mentorship programs to support their professional growth.
Working at Qualcomm means joining a team that pushes the boundaries of what's possible in technology. The company's work impacts lives globally through their innovations in mobile technology, AI, and connectivity solutions. This role offers the opportunity to collaborate with leading engineering experts and contribute to cutting-edge technology developments while building a rewarding career in hardware engineering.
Responsibilities For Network Packet Processing Core DV Sr Engineer
- Develop verification environment and testbench components
- Develop comprehensive test plans for unit level verification
- Verify design using directed and constrained random testing
- Write functional cover-groups and cover-points for coverage closure
- Perform RTL code coverage and gate level simulations
- Work with Systems, Design, SoC team, SW team, Validation & DFT teams
- Conduct verification reviews and coverage closure
- Assist SOC team with IP Integration testing
- Post-Silicon Debugs with Design, Validation and SW teams
Requirements For Network Packet Processing Core DV Sr Engineer
- 2-5 years of strong experience in digital front end ASIC design verification
- Bachelors or Masters Degree in Engineering in Electronics, VLSI, Communications or related field
- Expertise in System Verilog and UVM based verification
- Strong understanding of AHB, AXI and other bus protocols
- Understanding of TCP/IP Packet Processing Algorithms
- Good communication skills
- Self-motivated with good teamwork attitude
Benefits For Network Packet Processing Core DV Sr Engineer
- World-class health coverage for employees and dependents
- Financial planning and future preparation programs
- Emotional/mental strength and resilience support
- Wellbeing programs and resources
- Continuous learning and development programs
- Tuition reimbursement
- Mentorship programs
