Principal Design Verification Engineer (Coherent Interconnect)

Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL) are seeking a Principal Design Verification Engineer to join their System IP team. This role focuses on functional verification of System IP including coherent interconnect, caches, and dynamic memory controllers. As a principal engineer, you'll be responsible for architecting and building reusable testbenches, driving best practices, and providing technical leadership while maintaining hands-on involvement in project execution.

The position is part of Samsung's System IP team, which develops proprietary coherent interconnect and memory controllers deployed in high-volume products. The team plays a crucial role in influencing product roadmap for market-leading system IP solutions, focusing on system modeling capability based on optimization and use-case-driven analysis for gaming and computational photography applications.

The ideal candidate will bring 20+ years of experience (with Bachelor's) or equivalent education/experience combination, including deep expertise in design verification, testbench architecture, and ARM protocols. You'll work in a collaborative environment with opportunities to mentor junior team members while solving complex technical challenges in semiconductor product development.

This role offers competitive compensation ranging from $216,521 to $359,527, along with comprehensive benefits including medical insurance, 401(k), tuition assistance, and various other perks. Join Samsung's pursuit of excellence in advanced semiconductor technology, working on products that impact millions of users worldwide.