Principal Design Verification Engineer (Coherent Interconnect)

Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL) are seeking a Principal Design Verification Engineer to join their System IP team. This role focuses on the functional verification of System IP including coherent interconnect, caches, and dynamic memory controllers. The position offers an opportunity to work on cutting-edge semiconductor technology for high-performance computing devices across mobile, automotive, and custom market segments.

The ideal candidate will serve as a technical leader and hands-on contributor, bringing extensive experience in Design Verification and testbench architecture. They will be responsible for architecting reusable testbenches, driving best practices, and ensuring the quality of complex semiconductor products. The role involves collaboration with various teams including designers, SoC teams, and physical design teams.

The System IP team develops proprietary coherent interconnect and memory controllers deployed in high-volume products. They influence product roadmaps for market-leading system IP solutions, focusing on system modeling capability based on optimization and use-case-driven analysis. The team works in a collaborative environment that encourages innovation and technical growth.

Samsung offers a comprehensive benefits package including medical, dental, vision, life insurance, 401(k), and various other perks. The base salary range is $216,521 to $359,527, with additional benefits including MBO bonus compensation and potential long-term incentive plans. This is an excellent opportunity for an experienced verification engineer to make significant contributions to world-class memory subsystem development while working for a global technology leader.