Sr. Memory Controller Micro-Architect (Principal Engineer)

Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL) are seeking a Senior Memory Controller Micro-Architect to join their System IP team. This role focuses on developing proprietary coherent interconnect and memory controllers for high-performance computing devices across mobile, automotive, and custom market segments.

As a Principal Engineer, you'll lead the design and development of cutting-edge memory controller technologies including LPDDR5, LPDDR6, and Processing in Memory (PIM). The position requires deep expertise in memory controller micro-architecture, RTL design, and performance/power optimization. You'll work with a global team to transform innovative ideas into next-generation memory technologies.

The role offers an opportunity to work on full technology development cycles, collaborating with system architects, verification teams, and performance/power specialists. You'll be responsible for driving micro-architecture development, RTL design, debug, and timing closure for custom memory controllers while ensuring adherence to JEDEC standards.

Samsung offers a comprehensive benefits package including medical, dental, vision insurance, 401(k), tuition assistance, and various incentive programs. The base salary range is $216,521 to $359,527, with additional benefits including MBO bonus compensation and long-term incentive plans.

This position is based in either Austin, TX or San Jose, CA, requiring on-site presence. The role demands 20+ years of experience (or equivalent with advanced degrees) and deep technical expertise in memory technologies, ASIC design flow, and various programming languages. If you're passionate about logic design and innovation, and thrive in a fast-paced, global team environment, this role offers an excellent opportunity to shape the future of memory technology at a world-leading semiconductor company.