Design Verification Engineer (Silicon Engineering)
Description For Design Verification Engineer (Silicon Engineering)
SpaceX is seeking a Design Verification Engineer to join their Silicon Engineering team in Redmond, WA. This role is crucial for developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe, specifically supporting the Starlink satellite constellation project.
The position offers an exciting opportunity to work alongside world-class cross-disciplinary teams in systems, firmware, architecture, design, validation, and product engineering. You'll be directly contributing to SpaceX's mission of making reliable internet connectivity available globally through the Starlink network.
As a Design Verification Engineer, you'll be responsible for digital ASIC and FPGA verification at both block and system levels. Key responsibilities include developing SystemVerilog testbench infrastructure, executing test plans, and automating test case generation using Python and MATLAB. You'll also be involved in pre-silicon verification and post-silicon validation activities.
The ideal candidate should have at least 2 years of experience in design verification and test bench development, with a bachelor's degree in electrical engineering, computer science, or computer engineering. Strong problem-solving skills and experience with verification methodologies such as UVM are highly valued.
SpaceX offers a competitive compensation package ranging from $122,500 to $170,000 per year, depending on experience level. The company provides comprehensive benefits including medical coverage, 401(k), stock options, and various other perks. This role requires ITAR compliance, meaning candidates must be U.S. citizens, permanent residents, refugees, or asylees.
Join SpaceX in their mission to revolutionize space technology and global connectivity while working with cutting-edge technology in a dynamic, fast-paced environment. This is an opportunity to be part of a team that's literally changing the world through advanced space and communications technology.
Responsibilities For Design Verification Engineer (Silicon Engineering)
- Responsible for digital ASIC and/or FPGA verification at block and system level
- Write and review test plans, develop test harnesses and test sequences
- Develop SystemVerilog testbench infrastructure for testing designs, including DSP blocks
- Responsible for test plan execution, running regressions, code and functional coverage closure
- Automate test case generation using Python and MATLAB programs
- Contribute towards pre-silicon verification, chip bring-up and post-silicon validation
Requirements For Design Verification Engineer (Silicon Engineering)
- Bachelor's degree in electrical engineering, computer science or computer engineering
- 2+ years of experience with design verification and test bench development
- Must be willing to work extended hours and weekends as needed
- Must be a U.S. citizen, permanent resident, refugee, or asylee due to ITAR requirements
Benefits For Design Verification Engineer (Silicon Engineering)
- Medical, vision, and dental coverage
- 401(k) retirement plan
- Short & long-term disability insurance
- Life insurance
- Paid parental leave
- 3 weeks paid vacation
- 10+ paid holidays per year
- 5 days sick leave per year
- Stock options
- Employee Stock Purchase Plan
- Long-term incentives
Jobs Related To SpaceX Design Verification Engineer (Silicon Engineering)
