Design Verification Engineer (Silicon Engineering)
Description For Design Verification Engineer (Silicon Engineering)
SpaceX is seeking a Design Verification Engineer to join their Silicon Engineering team in Sunnyvale, CA. This role is crucial for the development of next-generation FPGAs and ASICs that will be deployed in space and ground infrastructures supporting the Starlink satellite constellation.
The position offers an exciting opportunity to work on cutting-edge technology that's literally changing the way the world connects. As part of SpaceX's mission to make humanity a multi-planetary species, you'll be working alongside world-class cross-disciplinary teams in systems, firmware, architecture, design, validation, and product engineering.
The role involves comprehensive verification responsibilities, from writing test plans to developing complex SystemVerilog testbenches. You'll be working with both UVM and non-UVM frameworks, automating test case generation using Python and MATLAB, and contributing to pre-silicon verification through post-silicon validation.
This is an ideal position for someone with a strong background in electrical engineering or computer science, with at least 2 years of experience in design verification. The role offers competitive compensation ranging from $130,000 to $180,000 depending on level and experience, along with comprehensive benefits including medical coverage, 401(k), stock options, and paid time off.
SpaceX offers a unique environment where your work will directly impact the future of space exploration and global connectivity. The company's focus on innovation and pushing technological boundaries makes this an exceptional opportunity for engineers who want to be part of something truly revolutionary. The role requires ITAR compliance and a willingness to work extended hours when needed, reflecting the ambitious nature of SpaceX's missions.
Responsibilities For Design Verification Engineer (Silicon Engineering)
- Responsible for digital ASIC and/or FPGA verification at block and system level
- Write and review test plans, develop test harnesses and test sequences
- Develop SystemVerilog testbench infrastructure for testing designs
- Responsible for test plan execution, running regressions, code and functional coverage closure
- Automate test case generation using Python and MATLAB programs
- Contribute towards pre-silicon verification, chip bring-up and post-silicon validation
Requirements For Design Verification Engineer (Silicon Engineering)
- Bachelor's degree in electrical engineering, computer science or computer engineering
- 2+ years of experience with design verification and test bench development
- Must be willing to work extended hours and weekends as needed
- Must meet ITAR requirements
Benefits For Design Verification Engineer (Silicon Engineering)
- Medical, vision, and dental coverage
- 401(k) retirement plan
- Short & long-term disability insurance
- Life insurance
- Paid parental leave
- 3 weeks paid vacation
- 10+ paid holidays per year
- 5 days sick leave per year
- Stock options
- Employee Stock Purchase Plan
- Long-term incentives
