FPGA/ASIC Design Engineer (Silicon Engineering)
Description For FPGA/ASIC Design Engineer (Silicon Engineering)
SpaceX, a pioneering space technology company, is seeking an FPGA/ASIC Design Engineer to join their Silicon Engineering team working on the revolutionary Starlink project. This role offers a unique opportunity to work at the intersection of space technology and advanced chip design, developing cutting-edge solutions that will help bring reliable internet access to millions worldwide.
The position involves working on next-generation FPGAs and ASICs that will be deployed both in space and in ground infrastructure globally. As part of the role, you'll collaborate with world-class cross-disciplinary teams, including systems, firmware, architecture, design, validation, and product engineering specialists. Your work will directly impact the expansion and enhancement of the Starlink network's capabilities.
The ideal candidate should have a strong background in digital design, with experience in ASIC/FPGA development and RTL coding using Verilog/SystemVerilog. You'll be responsible for the entire design process, from high-level architectural discussions to detailed implementation and validation. The role requires expertise in optimization for power, performance, and area, as well as familiarity with various EDA tools and design flows.
SpaceX offers a comprehensive benefits package including competitive base salary ($120,000-$170,000 based on level), equity opportunities, medical/dental/vision coverage, 401(k), paid parental leave, and various other perks. The company culture emphasizes innovation, problem-solving, and direct contribution to humanity's space exploration goals.
This position requires ITAR compliance (must be a U.S. citizen, permanent resident, refugee, or asylee) and willingness to work extended hours when needed. If you're passionate about pushing the boundaries of technology and want to be part of a team that's literally reaching for the stars, this role offers an exceptional opportunity to make a meaningful impact in space technology advancement.
Responsibilities For FPGA/ASIC Design Engineer (Silicon Engineering)
- Design digital ASICs and/or FPGAs for Starlink projects, implementing complex SoC blocks and SoC integration tasks
- Implement or integrate design blocks using Verilog/SystemVerilog
- Optimize designs for power, performance and area
- Participate in the design process from high-level concepts to micro architecture
- Participate in all phases of ASIC and/or FPGA design flow
- Work with ASIC backend/implementation teams
- Bring-up and validate ASICs and FPGAs in the lab
- Collaborate with software engineers in developing production software
Requirements For FPGA/ASIC Design Engineer (Silicon Engineering)
- Bachelor's degree in electrical engineering, computer engineering or computer science
- 2+ years of experience working with ASICs or FPGAs
- Experience designing digital ASICs and/or FPGAs
- Experience writing RTL in Verilog or SystemVerilog
- Experience with EDA tools
- Experience with scripting
- Must be willing to work extended hours and weekends as needed
- Must be a U.S. citizen, permanent resident, refugee, or asylee (ITAR requirement)
Benefits For FPGA/ASIC Design Engineer (Silicon Engineering)
- Medical, vision, and dental coverage
- 401(k) retirement plan
- Short & long-term disability insurance
- Life insurance
- Paid parental leave
- 3 weeks paid vacation
- 10+ paid holidays per year
- 5 days sick leave per year
- Stock options
- Employee Stock Purchase Plan
- Long-term incentives
- Discretionary bonuses
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