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SOC/ASIC Physical Design Engineer (Silicon Engineering)

SpaceX is a space exploration company developing technologies to enable human life on Mars and deploying Starlink, the world's largest satellite constellation for global internet access.
$130,000 - $180,000
Embedded
Mid-Level Software Engineer
In-Person
5,000+ Employees
2+ years of experience
Space

Description For SOC/ASIC Physical Design Engineer (Silicon Engineering)

SpaceX is revolutionizing space technology with the ultimate goal of enabling human life on Mars. As part of their Starlink initiative, which is the world's largest satellite constellation providing fast, reliable internet worldwide, they are seeking a SOC/ASIC Physical Design Engineer to join their Silicon Engineering team.

The role involves working on cutting-edge next-generation ASICs for deployment in space and ground infrastructures globally. You'll be part of world-class cross-disciplinary teams, developing chips that enable connectivity in previously underserved areas. Your work will directly impact the expansion and performance of the Starlink network.

The position requires expertise in physical implementation steps, methodology development, and close collaboration with the ASIC design team. You'll be responsible for various aspects of chip design, from synthesis to signoff checks, while working in a dynamic environment that pushes the boundaries of space technology.

SpaceX offers a comprehensive benefits package including medical, dental, and vision coverage, 401(k), stock options, ESPP, paid parental leave, and 3 weeks of vacation. The compensation is competitive, ranging from $130,000 to $180,000 depending on level and experience.

This is an opportunity to be part of a mission-driven company that's making space exploration and global connectivity a reality. The role requires a combination of technical expertise, problem-solving skills, and the ability to work in a fast-paced, innovative environment.

Last updated 3 hours ago

Responsibilities For SOC/ASIC Physical Design Engineer (Silicon Engineering)

  • Perform partition synthesis and physical implementation steps
  • Develop/improve physical design methodologies and automation scripts
  • Collaborate with ASIC design team on architectural feasibility studies
  • Resolve design/timing/congestion and flow issues
  • Run, debug, and fix signoff closure issues

Requirements For SOC/ASIC Physical Design Engineer (Silicon Engineering)

Python
Linux
  • Bachelor's degree in electrical engineering, computer engineering or computer science
  • 2+ years of professional experience working with ASICs and/or physical design flow development
  • Must be willing to work extended hours and weekends as needed
  • Must be a U.S. citizen, permanent resident, refugee, or asylee (ITAR requirements)

Benefits For SOC/ASIC Physical Design Engineer (Silicon Engineering)

Medical Insurance
Dental Insurance
Vision Insurance
401k
Equity
Parental Leave
  • Medical Insurance
  • Dental Insurance
  • Vision Insurance
  • 401k
  • Stock options
  • Employee Stock Purchase Plan
  • Paid parental leave
  • 3 weeks paid vacation
  • 10+ paid holidays
  • 5 days sick leave

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