SOC/ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering)
Description For SOC/ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering)
SpaceX, a pioneering space exploration company, is seeking a talented SOC/ASIC Timing Signoff & Front-End Implementation Engineer to join their Silicon Engineering team. This role is crucial in developing cutting-edge ASICs that will be deployed in both space and ground infrastructures globally, supporting the ambitious Starlink project - the world's largest satellite constellation providing high-speed internet access worldwide.
The position offers an exciting opportunity to work alongside world-class cross-disciplinary teams, including systems, firmware, architecture, design, validation, and product engineering specialists. You'll be at the forefront of developing advanced timing and noise signoff flows, implementing sophisticated timing closure methodologies, and ensuring the reliability of critical space-bound hardware.
The role combines deep technical expertise in ASIC design with the broader mission of enabling global connectivity in previously underserved areas. You'll be responsible for developing and supporting automated block and full chip level timing flows, defining signoff criteria, and working on timing optimization for next-generation chips. The position requires strong analytical skills, expertise in static timing analysis, and proficiency in various scripting languages.
SpaceX offers a comprehensive benefits package including medical, dental, and vision coverage, 401(k) retirement plan, equity opportunities, and paid time off. The compensation is competitive, ranging from $120,000 to $170,000 based on experience and expertise. This is an excellent opportunity for someone passionate about pushing the boundaries of silicon engineering while contributing to SpaceX's mission of making humanity a multi-planetary species.
The ideal candidate will have a bachelor's degree in electrical or computer engineering, experience with high-performance SOC designs, and knowledge of deep sub-micron FinFET technology nodes. The position requires occasional travel (less than 10%) and may involve extended hours during critical project phases. Due to ITAR requirements, candidates must be U.S. citizens, permanent residents, or eligible for required authorizations.
Responsibilities For SOC/ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering)
- Develop/support automated block and full chip level advanced timing/noise signoff flows
- Define block and full chip timing signoff criterion and methodology
- Develop/support signoff STA timing/power optimization engineering change order flows
- Work with systems architecture, SOC integration, and verification teams
- Generate block timing budgets, clock and I/O context files
- Debug and fix constraint correlation issues
- Develop clock network simulation and jitter analysis methodologies
Requirements For SOC/ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering)
- Bachelor's degree in electrical engineering, computer engineering or computer science
- Experience in static timing analysis and/or timing closure of high-performance SOC designs
- Full chip and block level STA tapeout experience
- Knowledge of deep sub-micron FinFET technology nodes
- Experience with memories, I/Os, Analog IPs, SerDes, DDR
- Excellent scripting skills (csh/bash, Perl, Python, TCL, Makefile)
- Must be willing to travel when needed (typically <10%)
- Must be U.S. citizen, permanent resident, or eligible for required authorizations
Benefits For SOC/ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering)
- Medical, vision, and dental coverage
- 401(k) retirement plan
- Short & long-term disability insurance
- Life insurance
- Paid parental leave
- 3 weeks paid vacation
- 10+ paid holidays per year
- 5 days sick leave
- Stock options
- Employee Stock Purchase Plan
- Discretionary bonuses
