SpaceX is seeking a Senior ASIC Design Engineer to join their Silicon Engineering team, focusing on developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. This role is crucial for the Starlink project, the world's most advanced broadband internet system, which is currently providing fast, reliable internet to millions of users worldwide.
The position offers an opportunity to work alongside world-class cross-disciplinary teams in systems, firmware, architecture, design, validation, and product engineering. You'll be responsible for developing sophisticated hardware solutions that enable connectivity in previously underserved areas, directly contributing to SpaceX's mission of making high-speed internet accessible globally.
As a Senior ASIC Design Engineer, you'll be involved in all aspects of the design process, from architectural planning to silicon bring-up. Key responsibilities include implementing complex SoC blocks, performing architectural trade-off analyses, and working with Verilog/SystemVerilog for design implementation. The role requires expertise in ASIC/FPGA design flows, including synthesis, timing closure, and ECO processes.
The position offers a competitive compensation package ranging from $160,000 to $220,000 per year, along with comprehensive benefits including medical coverage, 401(k), stock options, and generous paid time off. This is an excellent opportunity for experienced hardware engineers who want to make a significant impact on global connectivity infrastructure while working at the forefront of space technology.
SpaceX's unique position as a leader in space technology and satellite communications makes this role particularly exciting for engineers who want to push the boundaries of what's possible in ASIC design while contributing to a mission that aims to transform global internet access. The work environment is dynamic and fast-paced, requiring adaptability and a passion for solving complex technical challenges.