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Staff Verification Methodology / CAD Engineer

Toronto-based startup building the world's highest performance pure-digital AI inference chip with groundbreaking architecture.
$150,000 - $250,000
Embedded
Staff Software Engineer
Hybrid
101 - 500 Employees
10+ years of experience
AI · Hardware
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Description For Staff Verification Methodology / CAD Engineer

Untether AI, a Toronto-based startup with a $125 million Series B funding, is revolutionizing the AI industry with their groundbreaking pure-digital AI inference chip architecture. The company is seeking a Staff Verification Methodology / CAD Engineer to join their diverse and welcoming team. This role is crucial in shaping the future of AI chip design through innovative verification methodologies.

The position offers an opportunity to work with cutting-edge technology that delivers unparalleled performance and energy efficiency in AI inference. As the CAD DV Engineer, you'll be responsible for defining verification flows, leading EDA tool evaluations, and implementing verification frameworks. The role requires extensive experience in both design verification and CAD areas, with a focus on RTL Simulation, Formal Verification, and various EDA tools.

The company culture emphasizes diversity, inclusivity, and professional growth, welcoming candidates who show both capability and potential. They offer competitive benefits including stock options, comprehensive health benefits, and flexible vacation policies. The hybrid work environment allows for collaboration with team members across Canada, the US, and internationally.

This is an exceptional opportunity for an experienced engineer to contribute to groundbreaking AI technology while working with a team of scientists, engineers, and entrepreneurs. The company's recent funding and existing customer base demonstrate strong market validation and promising growth potential.

Last updated 3 months ago

Responsibilities For Staff Verification Methodology / CAD Engineer

  • Define the design verification flow
  • Lead EDA tools evaluation process and roll-out
  • Architect and implement verification framework
  • Champion infrastructure and methodology improvements

Requirements For Staff Verification Methodology / CAD Engineer

Python
Linux
  • 10+ years of experience
  • Hands-on knowledge of RTL Simulation and Formal Verification flows
  • Knowledge of UVM and SystemVerilog
  • Experience with verification tasks - test plan development, test bench development, simulation/waveform debug, coverage analysis
  • Working with EDA tools in the design verification industry
  • Developing flows and scripts to support EDA tools
  • Experience driving vendors AEs to resolve technical issues
  • Excellent programming and Unix skills (Python, Makefiles, Shell, TCL)
  • Minimum BS degree in EE/CE/CS, or equivalent

Benefits For Staff Verification Methodology / CAD Engineer

Medical Insurance
Dental Insurance
Vision Insurance
Equity
  • 20 vacation days
  • Strong health and extended health benefits
  • Unlimited sick days
  • Stock options

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