Design Verification Engineer, Lab126
Description For Design Verification Engineer, Lab126
Amazon's Lab126 is seeking a talented Design Verification (DV) Engineer to join their advanced architecture team. This role offers an exciting opportunity to work on cutting-edge hardware designs that enhance Amazon's device ecosystem. As a DV Engineer, you'll be at the forefront of defining verification methodologies and implementing comprehensive test plans for advanced functional blocks.
The position involves close collaboration with multi-disciplinary teams, including Product Design, Audio Technology, Computer Vision, Hardware Engineering, and Software Engineering. You'll play a crucial role in architecting and implementing complex functional blocks that enable the development of world-class hardware devices.
The ideal candidate should possess strong expertise in RTL development environments and modern hardware description languages. Experience with SystemVerilog, UVM, and coverage-driven verification is essential. You'll be responsible for creating test benches, debugging code, and ensuring the functional correctness of design blocks through various verification methods.
This role offers the opportunity to work with state-of-the-art verification platforms, including simulation, emulation, and prototyping environments. You'll be involved in all aspects of the verification process, from methodology definition to test plan development and coverage analysis.
Amazon offers a competitive compensation package, comprehensive benefits, and the chance to work with cutting-edge technology in a dynamic, fast-paced environment. Join us in shaping the future of consumer electronics and be part of a team that delivers innovative solutions used by millions of customers worldwide.
Responsibilities For Design Verification Engineer, Lab126
- Define verification methodology and implement test plans for advanced functional blocks
- Design world class hardware and software
- Create and enhance constrained-random verification environments using SystemVerilog and UVM
- Debug tests with design engineers
- Close coverage measures to identify verification holes
- Participate in test plan and coverage reviews
- Integrate 3rd party IPs/VIPs and transactors
- Perform IP/SOC bringup in simulation, emulation and prototyping environments
Requirements For Design Verification Engineer, Lab126
- Bachelor's degree or higher in EE, CE, or CS
- 7+ years practical semiconductor design verification experience
- Experience with System Verilog, UVM, assertions and coverage driven verification
- Experience using multiple verification platforms
- Experience defining verification methodologies
- Experience with test plan development and test bench infrastructure
- Experience with writing directed/constrained-random tests
- Experience with industry standard tools and scripting languages (Python or Perl)
- Excellent verbal and written communication skills
Benefits For Design Verification Engineer, Lab126
- Comprehensive medical, dental, and vision coverage
- Parental leave benefits
- Disability accommodations available
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