Sr. ASIC Design Verification Engineer
Description For Sr. ASIC Design Verification Engineer
Project Kuiper, an ambitious Amazon initiative, is seeking a Senior ASIC Design Verification Engineer to join their satellite communications team. This role is part of a groundbreaking project aimed at providing high-speed broadband connectivity to underserved communities worldwide through a constellation of Low Earth Orbit satellites.
The position offers an exceptional opportunity to work on cutting-edge wireless solutions with minimal legacy constraints. You'll be part of the team responsible for defining and implementing digital chip SOCs for satellite communications and Amazon gateways. The role combines advanced verification methodologies with state-of-the-art ASIC development.
Key responsibilities include implementing sophisticated verification environments, developing test plans, and ensuring functional correctness through formal verification. You'll work with UVM, SystemC, and DPI-C while collaborating with design and communication systems teams. The position requires expertise in verification of communication systems and proficiency in various programming languages and tools.
The compensation is highly competitive, ranging from $143,300 to $247,600, reflecting Amazon's commitment to attracting top talent. The role is available in several tech hubs including Austin, Sunnyvale, Redmond, and San Diego, offering flexibility in location choice.
This is an ideal opportunity for experienced verification engineers who want to make a significant impact on global connectivity while working with cutting-edge technology. The position offers comprehensive benefits including medical, dental, and vision insurance, along with the chance to work on technology that will help bridge the digital divide globally.
Due to export control requirements, candidates must be U.S. citizens, permanent residents, or have refugee/asylum status. The role requires a minimum of 7 years of verification experience and 3+ years with UVM, C, and scripting, making it perfect for senior engineers looking to advance their careers in satellite communications technology.
Responsibilities For Sr. ASIC Design Verification Engineer
- Implement state of the art verification environment to test RTL against reference Matlab/C models
- Develop detailed test plans and write tests, run regressions, collect coverage matrices
- Participate in validation of ASIC implementations in Verilog/SystemVerilog
- Run formal verification of complex blocks
- Work with design and communication systems team on system level verification using UVM, SystemC and DPI-C
- Develop automated environment for running regressions
Requirements For Sr. ASIC Design Verification Engineer
- Bachelor's degree in Electrical / Communications Engineering or Computer Science, or related field, or equivalent experience
- 7+ years in verification preferably in communication systems
- 3+ years in UVM, C, and scripting
- Must be a U.S. citizen or national, U.S. permanent resident, or lawfully admitted into the U.S. as a refugee or granted asylum
Benefits For Sr. ASIC Design Verification Engineer
- Medical Insurance
- Dental Insurance
- Vision Insurance
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