CAD Engineer - Timing for Gate-Level Flows & Methodologies

Do you love creating elegant solutions to highly complex challenges? As part of Apple's Silicon Technologies group, you'll help design and manufacture next-generation, high-performance, power-efficient processors and system-on-chip (SoC). You'll be responsible for crafting and building the technology that fuels Apple's devices, ensuring they can seamlessly handle tasks beloved by millions.

As a member of the STA CAD team, you will be integral to improving Apple Silicon performance. Your role focuses on static timing methodologies, addressing timing challenges on advanced tech nodes through developing flows and methodologies used by all Apple Silicon teams. You'll drive timing analysis and closure for first-time-right silicon.

Key responsibilities include developing and maintaining gate-level STA flows, collaborating with design teams on timing issues, enhancing methodology efficiency, and working with EDA vendors. You'll need expertise in static timing analysis, programming skills (Python/Tcl), and deep understanding of SoC design timing constraints.

This role combines technical expertise with collaborative problem-solving, making you a crucial part of Apple's innovative silicon development team. You'll work at the intersection of hardware and software, ensuring Apple's processors meet the highest performance standards while maintaining power efficiency.

Join us to be part of a team that's revolutionizing processor technology and directly impacting millions of Apple users worldwide. Your work will help shape the future of Apple's custom silicon, driving the performance that makes Apple products stand out in the market.