Cellular SOC Design Verification Engineer - Entry Level

Apple's Silicon Engineering Group is seeking a passionate and self-driven Design Verification Engineer to join their cutting-edge Cellular SoC team. This role offers an exceptional opportunity to work on state-of-the-art Cellular SoCs within Apple's silicon design group.

As a Design Verification Engineer, you'll be central to verifying complex SOCs that deliver cellular solutions. Your responsibilities will include integrating sophisticated IP level DV environments, developing reusable UVM-based test benches, and implementing effective coverage-driven test suites. You'll work with cutting-edge tools and methodologies to ensure first-time-right chip designs.

This position offers extensive learning opportunities across large-scale SOC design, complex verification test benches, various SOC architectures, high-speed protocols, and industry-standard low power architecture. You'll gain expertise in best-in-class DV methodology, verification on accelerated platforms, Cellular protocol knowledge, and multi-chip SOC debug architecture.

Working at Apple, you'll receive competitive compensation including a base salary range of $121,900 to $183,600, plus opportunities for stock awards, bonuses, and comprehensive benefits. The role offers collaboration with diverse product development teams, pushing the boundaries of cellular systems technology and enhancing product experiences for customers worldwide.

Ideal candidates should possess a BS in EE or CS, strong object-oriented programming skills, and digital design knowledge. Experience with SystemVerilog, Python, or C++ is preferred. We value team players with excellent communication and problem-solving abilities who are eager to tackle diverse challenges.