Design Verification Engineer

A leading technology company that designs and develops consumer electronics, software, and services.
Cary, NC, USA
$140,000 - $220,000
Hardware
Senior Software Engineer
In-Person
5,000+ Employees
10+ years of experience
Hardware

Description For Design Verification Engineer

At Apple, we work every single day to craft products that enrich people's lives. As a Design Verification Engineer, you'll join our hardware team to work on challenges that no one has solved yet. You'll have the extraordinary opportunity to craft upcoming products that will delight millions of Apple's customers daily.

This role focuses on pre-silicon verification including establishing DV methodology, test-plan development, verification environment development, and ensuring bug-free first silicon for SoC/IP designs. You'll be responsible for developing scalable verification environments using SystemVerilog and UVM, creating comprehensive test plans, and implementing robust verification solutions.

You'll work with cutting-edge hardware designs, utilizing your expertise in verification methodologies and tools like simulators and waveform viewers. The role requires strong programming skills in SystemVerilog and scripting languages, along with deep understanding of hardware verification concepts.

As part of Apple's hardware team, you'll collaborate with world-class engineers to ensure the quality and reliability of Apple's innovative products. Your work will directly impact the development of next-generation hardware solutions that power Apple's ecosystem of devices.

This is an excellent opportunity for an experienced verification engineer who wants to work on challenging projects at the forefront of technology, contributing to products that impact millions of users worldwide. You'll be part of a team that values innovation, quality, and attention to detail in delivering exceptional hardware solutions.

Last updated 3 days ago

Responsibilities For Design Verification Engineer

  • Ensure bug-free first silicon for part of the SoC / IP
  • Develop detailed test and coverage plans based on micro-architecture
  • Develop verification methodology suitable for the IP
  • Create verification environment including stimulus, checkers, assertions, trackers, coverage
  • Execute verification plans including design bring-up and regression testing
  • Develop block, IP and SoC level test-benches
  • Track and report DV progress using metrics including bugs and coverage

Requirements For Design Verification Engineer

Python
  • BS degree in technical subject area with minimum 10 years of proven experience

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