FE Design and Timing Analysis Integration Engineer

Apple's wireless silicon development team is seeking a Front End and Timing Analysis Engineer to join their growing organization. This role is part of the wireless SoC team responsible for all aspects of wireless silicon development, with a focus on highly energy-efficient design and innovative technologies that enhance user experience at the product level.

The position involves working with a world-class vertically integrated engineering team spanning multiple disciplines including RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering.

As a Front End and Timing Analysis Engineer, you will be deeply involved in implementing high-performance, low-power wireless SoCs from RTL to final GDSII delivery. Your work will include generating chip/block level static timing constraints, synthesizing designs with UPF/DFT/BIST, and collaborating with design and PD teams to close timing on critical blocks.

The role requires expertise in static timing analysis flows and the ability to provide guidance for fixing violations. You'll also be responsible for timing optimization, functional ECO implementation, and establishing/improving CAD and design flow methodologies. Success in this position demands strong collaboration skills as you'll work with multi-disciplinary teams to ensure timely delivery of high-quality designs.

This is an excellent opportunity for someone who thrives in a fast-paced, challenging environment and enjoys cross-functional collaboration. The position offers competitive compensation ranging from $143,100 to $264,200, comprehensive benefits including medical coverage, retirement benefits, and equity opportunities through Apple's discretionary employee stock programs.