Formal Verification Engineer

Global technology company that designs, manufactures, and sells consumer electronics, software, and services.
Waltham, MA, USA
Hardware
Senior Software Engineer
In-Person
5,000+ Employees
10+ years of experience
Hardware
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Description For Formal Verification Engineer

Do you love creating elegant solutions to highly complex challenges? As part of Apple's Silicon Technologies group, you'll help design and manufacture next-generation, high-performance, power-efficient processors and system-on-chip (SoC). You'll be responsible for formal verification of various design blocks and IP's including CPU, Cellular and Connectivity IP, Audio and Image Processing IP, Neural Networks IP, Memory/DMA Controller, Security IP, and more. Working with the best Formal Verification team in the world, you'll be at the center of SoC design verification efforts, ensuring Apple products can seamlessly handle tasks beloved by millions. The role involves developing formal micro-architecture specifications, comprehensive verification plans, proving design properties, and creating innovative solutions for security verification. You'll work closely with world-class Security Enclave design engineers and contribute to crafting the technology that fuels Apple's devices. This position requires expertise in VLSI, digital logic design, formal verification methods, and a strong background in hardware specifications and verification tools. The ideal candidate will have excellent debugging skills, strong interpersonal abilities, and a passion for developing world-class formal verification solutions.

Last updated 8 days ago

Responsibilities For Formal Verification Engineer

  • Working with Apple Silicon's Security Enclave design engineers to develop formal micro-architecture specification
  • Developing comprehensive formal verification test plan including security requirement verification
  • Proving properties of the design, finding design bugs, and working with design teams
  • Crafting solutions for modelling security attacks and proving robustness of complex design micro-architectures
  • Developing and implementing re-usable and optimized formal models and verification code base
  • Architecting correct-by-construction design methodologies for improved formal verification efficiency

Requirements For Formal Verification Engineer

  • Bachelor's degree with a minimum of 10 years of relevant industry experience in silicon validation, silicon design, software engineering, or a related field
  • Hands on experience with VLSI and digital logic design and verification techniques
  • Knowledge and experience in interpreting hardware specifications
  • Proficiency in any scripting language with excellent debugging skills
  • Experience in using EDA formal tools
  • Temporal logic assertion-based languages such as SVA or PSL

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