Formal Verification Engineer

Apple is where individual imaginations gather together, committing to the values that lead to great work. Every new product we build, service we create, or Apple Store experience we deliver is the result of us making each other's ideas stronger.
Backend
Senior Software Engineer
In-Person
5+ years of experience
AI
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Description For Formal Verification Engineer

As a formal verification engineer at Apple, you'll be part of the Silicon Technologies group, working on designing and manufacturing next-generation, high-performance, power-efficient processors and system-on-chip (SoC). You'll be responsible for complete formal verification of single or multiple design blocks and IPs, including CPU, Cellular and Connectivity IP, Audio and Image Processing IP, Neural Networks IP, Memory/DMA Controller, Security IP, Peripheral IP, Interconnects, and Power management subsystems.

Key responsibilities include:

  • Collaborating with world-class design engineers to develop formal micro-architecture specifications
  • Formalizing the refinement from architecture to micro-architecture
  • Developing comprehensive formal verification test plans
  • Proving properties of the design, finding design bugs, and working closely with design teams
  • Crafting novel and creative solutions for verifying complex design micro-architectures
  • Developing and implementing re-usable and optimized formal models and verification code base
  • Architecting correct-by-construction design methodologies for improved formal verification efficiency and productivity

This role offers the opportunity to work with the best Formal Verification team in the world and gain experience being at the center of a System-on-a-chip (SoC) design verification effort. You'll have a critical impact on delivering high-quality functional products to millions of customers quickly.

Apple is committed to inclusion, diversity, and creating an environment where individual imaginations can thrive. They offer various benefits and are dedicated to creating innovative products that change lives for the better.

Last updated 7 months ago

Responsibilities For Formal Verification Engineer

  • Develop formal micro-architecture specifications with design engineers
  • Formalize the refinement from architecture to micro-architecture
  • Develop comprehensive formal verification test plans
  • Prove properties of the design and find design bugs
  • Craft novel solutions for verifying complex design micro-architectures
  • Develop re-usable and optimized formal models and verification code base
  • Architect correct-by-construction design methodologies

Requirements For Formal Verification Engineer

Java
  • Bachelor's degree in electrical engineering, computer engineering, or related field
  • Hands-on experience with VLSI and digital logic design and verification techniques or formal methods and their application to hardware, software, or systems
  • Interest in learning and becoming an expert in SoC, CPU, GPU, or Cellular designs
  • Detail-oriented approach and desire to overcome challenges

Benefits For Formal Verification Engineer

  • Equal opportunity employer
  • Affirmative action for equal opportunity
  • Consideration for applicants with criminal histories
  • Reasonable accommodation for applicants with disabilities
  • Drug-free workplace

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