PHY RTL Design Engineer
Description For PHY RTL Design Engineer
Apple's wireless silicon development team is seeking a talented PHY RTL Design Engineer to join their growing organization. This role is part of the wireless SOC team responsible for all aspects of wireless silicon development, with a focus on highly energy-efficient design and innovative technologies that enhance user experience at the product level.
The position involves working with a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. The ideal candidate will be responsible for designing and implementing advanced signal processing algorithms for Wireless LAN communication systems.
As a Physical Layer design engineer, you will be architecting, designing, and verifying physical layer algorithms while collaborating with protocol, software, and systems teams to develop state-of-the-art wireless silicon for Apple products. The role requires expertise in signal processing intensive design for wireless communication SoCs, including specification writing, microarchitecture definition, and implementation of area and power-efficient designs.
Key responsibilities include developing MATLAB/C system models, creating power-efficient RTL logic designs, ensuring clean lint and CDC/RDC designs, and working on synthesis and timing constraints. The position offers the opportunity to work in a fast-paced, challenging environment while collaborating across different functional areas.
The role requires a minimum of 3 years of relevant industry experience, with a strong background in wireless PHY design engineering. Successful candidates will possess deep knowledge of fixed-point implementations, decoder systems, filter design, and modern energy-efficient design techniques. Experience with wireless standards such as IEEE 802.11, Bluetooth, or 3GPP is highly valued, along with proven experience in bringing logic designs into high-volume production.
Responsibilities For PHY RTL Design Engineer
- Develop signal processing intensive design for wireless communication SoCs
- Writing specifications and defining Microarchitecture based on MATLAB/C system model
- Architecting area and power efficient low latency designs
- Work with algorithm and software team to ensure performance and power efficiency
- Power and Area efficient RTL logic design, and DV support
- Running tools to ensure lint and CDC/RDC clean design
- Synthesis and timing constraints
- Design of signal processing Wireless protocols
Requirements For PHY RTL Design Engineer
- BS and 3+ years of relevant industry experience
- Strong fixed-point knowledge and extensive experience with bit-true cycle-accurate verifications
- Understanding of Decoders - Viterbi, LDPC, Polar
- Understanding of Filter design, multi-radix implementation
- Knowledge in modern design techniques and energy-efficient/low-power logic design
- Background in computer architecture
- Experience with FPGA and/or emulation platform desired
- Excellent communication skills – both written and oral
Benefits For PHY RTL Design Engineer
- Comprehensive medical and dental coverage
- Vision insurance
- Retirement benefits
- Employee stock programs
- Education reimbursement
- Discretionary bonuses
- Relocation assistance
- Employee Stock Purchase Plan
