Power UPF Methodology Engineer

Join Apple's Digital Design Engineering group and be part of an exciting silicon design team responsible for creating state-of-the-art ASICs. As a Power UPF Methodology Engineer, you'll drive transistor level power ERC sign-off and power intent-UPF implementation & verification on mobile SOCs. You'll work at the center of SOC design efforts, collaborating across teams to deliver functional products to millions of customers.

The role involves developing and supporting transistor level power ERC sign-off for digital and mixed signal designs, driving full-chip level power ERC sign-off, and implementing UPF verification for mobile SOCs. You'll work on making current power sign-off flows more robust while expanding power sign-off methodology for next-generation mobile products.

You'll collaborate with various teams, including CAD and physical design verification, to ensure successful power ERC and power intent flow implementation. This position requires strong technical expertise in ASIC design methodology, circuit fundamentals, and power analysis, combined with excellent communication skills to work effectively across different groups.

Working at Apple means being part of a team that turns imaginative ideas into reality, applying engineering fundamentals to create groundbreaking solutions. You'll have the opportunity to contribute to products that impact millions of users worldwide while working with cutting-edge technology in silicon design.