Timing Design Engineer

At Apple, we work every single day to craft products that enrich people's lives. As a Timing Design Engineer, you'll be joining a multifaceted group working on challenges that no one has solved yet. This role puts you at the center of PHY design efforts, collaborating with architecture, CAD, and logic design teams to deliver outstanding PHY designs.

As an ASIC STA Engineer, you'll be responsible for all aspects of SoC design timing, including timing sign-off, STA and sign-off flow development, and ownership of IP and block level timing constraints. You'll work closely with RTL designers to understand design intent and clock structure, with CAD teams to develop and understand flow, and with Physical design teams to achieve timing closure.

The role requires expertise in ASIC design timing closure flow and methodology, with at least 5+ years of experience in writing ASIC timing constraints and timing closure. You'll need proficiency in STA tools (Primetime), deep knowledge of timing corners/modes, process variations, and signal integrity issues. Strong scripting skills in Tcl and Perl are essential.

At Apple, you'll be part of a team that's changing the game in hardware design. You'll have access to comprehensive benefits including medical and dental coverage, retirement benefits, stock options, and education reimbursement. The base pay range for this role is between $175,800 and $312,200, with additional opportunities for equity and bonuses.

This is an opportunity to work on products that will impact millions of Apple customers worldwide. We're looking for a self-starter who's highly motivated and can communicate effectively with various teams. If you're passionate about solving complex timing challenges and want to be part of Apple's innovative hardware team, this role offers the perfect platform to make your mark.