HBM/DDR/SERDES DFT Verification Lead Engineer
Description For HBM/DDR/SERDES DFT Verification Lead Engineer
Broadcom's ASIC Product Division is seeking a highly skilled HBM/DDR/SERDES DFT Verification Lead Engineer for their San Jose and Fort Collins locations. This role focuses on ensuring the robustness and reliability of HBM, DDR, and SerDes designs through comprehensive Design for Test (DFT) verification strategies.
The position offers a competitive salary range of $107,000 - $190,000, along with comprehensive benefits including medical, dental, vision insurance, 401(k) matching, and equity compensation. The role requires either a Bachelor's degree with 8+ years of experience or a Master's degree with 6+ years of experience in Electrical/Electronic/Computer Engineering.
As a DFT Verification Lead Engineer, you'll be responsible for implementing and verifying DFT methodologies, collaborating with cross-functional teams, and driving innovation in testability solutions for 3nm IPs and beyond. The role requires expertise in analog DFT, MBIST, IEEE1687, and proficiency in scripting languages like Python, Perl, and TCL.
The ideal candidate will possess strong analytical and problem-solving skills, excellent communication abilities, and deep knowledge of analog and digital circuit design. You'll work with global teams, handle customer interactions, and contribute to silicon failure analysis and yield improvement efforts.
Broadcom, a global technology leader in semiconductor and infrastructure software solutions, offers a dynamic work environment with opportunities for professional growth and innovation. The company maintains a strong commitment to equality and diversity, considering qualified applicants regardless of background or protected characteristics.
Responsibilities For HBM/DDR/SERDES DFT Verification Lead Engineer
- Implement and verify DFT methodologies for HBM, DDR and SerDes designs
- Collaborate with design and architecture teams to identify testability requirements
- Utilize advanced simulation tools to verify DFT implementations
- Analyze DFT-related data and provide insights for design improvements
- Document verification processes, results, and best practices
- Work with STA and DI Engineers for test design closure
- Generate, verify & debug test vectors before tape release
- Validate & debug test vectors on ATE during silicon bring up
- Assist with silicon failure analysis and yield improvement
- Interface with customers and global engineering teams
- Debug customer returned parts on the ATE
- Innovate DFT solutions for 3nm IPs & beyond
- Automate DFT & Test Vector Generation flows
Requirements For HBM/DDR/SERDES DFT Verification Lead Engineer
- Strong DFT background (Analog DFT, MBIST, IEEE1687)
- Experience in DFT verification with HBM, DDR, PCIE and SerDes IPs
- Understanding of DFT methodologies including scan, BIST, and ATPG
- Proficiency in simulation tools and scripting languages (Perl, Python, TCL, ruby)
- Excellent analytical and problem-solving skills
- Strong communication and teamwork abilities
- Solid knowledge in analog and digital circuit design
- Bachelor's in Electrical/Electronic/Computer Engineering with 8+ years experience or Master's with 6+ years experience
Benefits For HBM/DDR/SERDES DFT Verification Lead Engineer
- Medical insurance
- Dental insurance
- Vision insurance
- 401(k) with company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- Paid holidays
- Paid sick leave
- Vacation time
- Annual bonus
- Equity compensation
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