Mixed-Signal Design Verification Engineer
Description For Mixed-Signal Design Verification Engineer
Broadcom, a global leader in semiconductor and infrastructure software solutions, is seeking a Senior Mixed-Signal Design Verification Engineer to join their team in San Jose, CA. This is a highly visible role focused on ASIC development for data center connectivity applications.
The ideal candidate will bring 10+ years of experience in mixed signal design verification, along with an advanced degree in Electrical or Computer Engineering. You'll be working with cutting-edge technology, utilizing your expertise in SV UVM, verification coverage matrix, and industry-standard EDA tools from Synopsys/Cadence.
This role offers an excellent opportunity to work on complex technical challenges in mixed-signal design, including ADCs, DACs, PLLs, and SerDes. You'll be responsible for developing and implementing comprehensive verification strategies, working with regression tests, and ensuring quality through metric-driven verification plans.
The position comes with a competitive compensation package ranging from $141,000 to $225,000 annually, plus additional benefits including discretionary bonuses and equity compensation. Broadcom offers comprehensive benefits including medical, dental, and vision insurance, 401(k) with company matching, ESPP, and various leave benefits.
As part of Broadcom's innovative team, you'll have the opportunity to contribute to cutting-edge technology solutions while working in a collaborative environment that values technical excellence and creative problem-solving. The company's strong market position and continued growth provide excellent opportunities for career advancement and professional development.
Join a team that's pushing the boundaries of semiconductor technology and making a significant impact in the data center connectivity space. Your expertise in mixed-signal design verification will be crucial in ensuring the quality and reliability of Broadcom's advanced ASIC solutions.
Responsibilities For Mixed-Signal Design Verification Engineer
- Work on ASIC for data center connectivity applications
- Develop and maintain verification frameworks
- Implement metric driven verification plans
- Collaborate with cross-functional teams
Requirements For Mixed-Signal Design Verification Engineer
- MS or PhD in Electrical Engineering or Computer Engineering
- 10+ years of experience in mixed signal design verification
- Experience in SV UVM, SV RNM and verification coverage matrix
- Experience with writing regression tests, developing checker, writing assertions
- Experience with Verisium Manager
- Knowledge of analog mixed-signal building blocks (ADCs, DACs, PLLs and SerDes)
- Experience with generating randomized vectors for analog and digital behavioral model verification
- Knowledge of standard industry EDA tools - Synopsys/Cadence
- Experience with GLS with & without parasitic annotated simulations
- Experience in generating UVM RAL model
- Proficient with scripting languages like PERL, Python
- Strong written and verbal communication skills
- Excellent time and task management skills
Benefits For Mixed-Signal Design Verification Engineer
- Medical insurance
- Dental insurance
- Vision insurance
- 401(k) with company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- Paid holidays
- Paid sick leave
- Vacation time
- Paid Family Leave
- Annual discretionary bonus
- Equity compensation
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