Principal Verification Engineer
Description For Principal Verification Engineer
Broadcom is seeking an experienced Principal Verification Engineer to join their team in San Jose, CA. This senior-level position focuses on mixed-signal design verification for ASIC applications in data center connectivity. The role requires a blend of technical expertise in verification methodologies and hands-on experience with industry-standard tools and practices.
The ideal candidate will bring 10+ years of experience in mixed signal design verification, along with advanced education in Electrical or Computer Engineering. They will be responsible for developing and executing comprehensive verification strategies for complex ASIC designs, working with cutting-edge technology in the semiconductor industry.
Key technical requirements include expertise in SV UVM, verification coverage matrices, and proficiency with industry-standard EDA tools from Synopsys/Cadence. The role involves working with analog mixed-signal building blocks and requires strong programming skills in languages like Python and PERL.
Broadcom offers a competitive compensation package, with a base salary range of $141,000 - $225,000, plus potential annual bonuses and equity awards. The company provides comprehensive benefits including medical, dental, and vision insurance, 401(k) matching, and an Employee Stock Purchase Program.
This is an excellent opportunity for a seasoned verification engineer looking to work with a global technology leader in semiconductor design. The position offers the chance to work on challenging projects while contributing to cutting-edge technology solutions in data center connectivity.
Responsibilities For Principal Verification Engineer
- Work on ASIC for data center connectivity applications
- Develop and maintain verification frameworks
- Generate randomized vectors for analog and digital behavioral model verification
- Manage and execute verification plans
Requirements For Principal Verification Engineer
- MS or PhD in Electrical Engineering or Computer Engineering with 10+ years of experience in mixed signal design verification
- Hands on experience in SV UVM, SV RNM and verification coverage matrix
- Experience with writing regression tests, developing checker, writing assertions and developing metric driven verification plan
- Prior experience in setting up and maintaining regressions using Verisium Manager
- Familiarity with analog mixed-signal building blocks such as ADCs, DACs, PLLs and SerDes
- Hands-on knowledge of standard industry EDA tools - Synopsys/Cadence
- Experience with GLS with & without parasitic annotated simulations
- Prior experience in generating UVM RAL model
- Proficient with scripting languages like PERL, Python etc.
- Strong written and verbal communication skills
- Self-starter and team player
Benefits For Principal Verification Engineer
- Medical insurance
- Dental insurance
- Vision insurance
- 401(k) with company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- Paid holidays
- Paid sick leave
- Vacation time
- Annual discretionary bonus
- Equity awards
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