Staff IP DFT Verification Engineer
Description For Staff IP DFT Verification Engineer
Broadcom's ASIC Product Division is seeking an experienced Staff IP DFT Verification Engineer at their Bangalore Development Center. This role focuses on ensuring the robustness and reliability of HBM, DDR, and SerDes designs through comprehensive Design for Test (DFT) verification strategies.
The position requires a seasoned professional with 8+ years of experience (or 6+ with a Masters) in DFT verification, particularly with HBM, DDR, PCIE, and SerDes IPs. The ideal candidate will have strong expertise in DFT methodologies including scan, BIST, and ATPG, along with proficiency in simulation tools and scripting languages.
As a Staff Engineer, you'll be responsible for implementing and verifying DFT methodologies, collaborating with cross-functional teams, and driving innovation in test solutions for 3nm IPs and beyond. The role involves working with cutting-edge technology in semiconductor design and verification, offering opportunities to work on complex technical challenges.
Key aspects of the role include:
- Leading DFT verification efforts for advanced semiconductor designs
- Collaborating with global teams across different time zones
- Driving continuous improvement in test methodologies
- Contributing to silicon failure analysis and yield improvement
- Automating test vector generation flows
The position offers the opportunity to work with a global technology leader in semiconductor design, with access to state-of-the-art tools and technologies. You'll be part of a dynamic team working on next-generation semiconductor solutions, making this an excellent opportunity for someone looking to advance their career in semiconductor verification and test.
Broadcom offers a collaborative work environment and values diversity and inclusion, making it an ideal place for professionals looking to make significant contributions to semiconductor technology advancement. The role provides exposure to cutting-edge technology and the chance to work with industry experts while solving complex technical challenges in semiconductor design and verification.
Responsibilities For Staff IP DFT Verification Engineer
- Implement and verify DFT methodologies for HBM, DDR and SerDes designs
- Collaborate with design and architecture teams to identify testability requirements
- Utilize simulation tools to verify DFT implementations
- Analyze DFT-related data and provide insights for design improvements
- Document verification processes and results
- Generate, verify and debug test vectors before tape release
- Validate and debug test vectors on ATE during silicon bring up
- Assist with silicon failure analysis and yield improvement
- Interface with customers and global teams
- Debug customer returned parts on ATE
- Automate DFT & Test Vector Generation flows
Requirements For Staff IP DFT Verification Engineer
- Strong DFT background (Analog DFT, MBIST, IEEE1687)
- Experience in DFT verification with HBM, DDR, PCIE and SerDes IPs
- Understanding of DFT methodologies including scan, BIST, and ATPG
- Proficiency in simulation tools and scripting languages (Perl, Python, TCL, ruby)
- Knowledge in analog and digital circuit design
- Excellent problem solving and debug skills
- Bachelors in Electrical/Electronic/Computer Engineering with 8+ years experience or Masters with 6+ years experience
- Strong communication and teamwork abilities
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