Staff SRAM Design Engineer
Description For Staff SRAM Design Engineer
Broadcom is seeking a Staff SRAM Design Engineer to join their semiconductor design team in Bangalore. This is a senior-level position focused on designing and developing advanced memory solutions using cutting-edge technologies. The role involves leading the development of SRAM and Register file compilers across various technology nodes (7FF/5FF/3FF/2nm), requiring deep expertise in circuit design and simulation.
The position demands strong technical skills in CMOS circuit design, memory architecture, and hands-on experience with industry-standard EDA tools. You'll be responsible for critical aspects of memory design, from bitcell and sense amplifier design to comprehensive margin analysis and performance optimization. The role requires collaboration with cross-functional teams and the ability to drive projects from specification to final release.
This is an excellent opportunity for an experienced engineer to work at a global technology leader in semiconductor design. You'll be working with state-of-the-art technology nodes and contributing to the development of high-performance memory solutions. The position offers the chance to work on challenging technical problems while leading and mentoring team members.
Broadcom's position as a major player in the semiconductor industry, combined with their commitment to innovation and technical excellence, makes this an attractive role for someone looking to advance their career in SRAM design and memory architecture. The company's global presence and diverse project portfolio provide excellent opportunities for professional growth and impact.
Responsibilities For Staff SRAM Design Engineer
- Lead design and development of Single/Multiport SRAM, Register file compilers in 7FF/5FF/3FF/2nm Technologies
- Circuit design/simulation of key components like bitcell, WL decoder, Sense Amplifier, Column decoder and control logic
- Develop critical path and characterization flow for detailed margin simulations
- Perform statistical analysis of Bit-Cell, Sense Amplifier and Self Time Blocks
- Design tuning/optimizations, margin analysis and sign-off for complete compiler
- Conduct logic simulations and timing analysis of key paths in high speed memory design
- Coordinate with various teams including design, modeling, layout and verification teams
Requirements For Staff SRAM Design Engineer
- Expertise in high speed/low power CMOS circuit design, clocking scheme, static and dynamic logic circuits
- Experience in designing and driving memory compilers specifications to final release
- Hands-on experience with Cadence/Mentor schematic/layout editor tools
- Experience with Circuit simulation, MC analysis and waveform viewer tools (HSPICE, HSIM, XA, FinSim, XARA, nWave, WV)
- Experience in Skill/Perl/Python Scripting
- Understanding of layout design issues and process issues/limitation in FINFET
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