ASIC Engineering Technical Lead :: DFT/MBIST/ATPG/Scan Insertion :: Exp 12+ Years
Description For ASIC Engineering Technical Lead :: DFT/MBIST/ATPG/Scan Insertion :: Exp 12+ Years
Join Cisco's Common Hardware Group (CHG) as an ASIC Engineering Technical Lead focusing on Design-for-Test in Bangalore, India. CHG, with ~2,100 employees across 16 countries, delivers silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. You'll be part of the Silicon One development organization, working on groundbreaking next-generation networking chips. The role involves implementing DFT features, developing innovative test solutions, and collaborating with multi-functional teams on complex ASIC designs.
As a Technical Lead, you'll drive DFT and quality processes through implementation and post-silicon validation phases. The position requires expertise in Jtag protocols, Scan and BIST architectures, ATPG tools, and system verification. You'll work with cutting-edge technologies and contribute to Cisco's unified routing and switching portfolio that serves enterprises, service providers, and data centers worldwide.
This is an excellent opportunity for an experienced professional to shape the future of networking hardware at a company that values innovation and inclusive culture. Cisco offers comprehensive benefits, including medical, dental, vision insurance, 401(k) with matching, and various time-off programs. The company embraces diversity, encourages creativity, and provides opportunities for professional growth in a collaborative environment.
Responsibilities For ASIC Engineering Technical Lead :: DFT/MBIST/ATPG/Scan Insertion :: Exp 12+ Years
- Implementing Hardware Design-for-Test (DFT) features for ATE, in-system test, debug and diagnostics
- Developing innovative DFT IP in collaboration with multi-functional teams
- Integration and validation of Test logic in implementation and post silicon validation flows
- Creating innovative Hardware DFT & physical design aspects for new silicon device models
- Working with design/design-verification and PD teams
Requirements For ASIC Engineering Technical Lead :: DFT/MBIST/ATPG/Scan Insertion :: Exp 12+ Years
- Bachelor's or Master's Degree in Electrical or Computer Engineering with 10+ years of experience
- Knowledge of latest innovative trends in DFT, test and silicon engineering
- Experience with Jtag protocols, Scan and BIST architectures
- Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime
- System Verilog Logic Equivalency checking skills
- Experience with Gate level simulation and debugging
- Post-silicon validation and debug experience
- Strong verbal skills
- Scripting skills in Tcl, Python/Perl
Benefits For ASIC Engineering Technical Lead :: DFT/MBIST/ATPG/Scan Insertion :: Exp 12+ Years
- Medical insurance
- Dental insurance
- Vision insurance
- 401(k) with company match
- Short and long-term disability coverage
- Basic life insurance
- Paid holidays
- Vacation time
- Sick time off
- Volunteer time off
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