Staff DFT Engineer
Description For Staff DFT Engineer
Eliyan, a leading chiplet startup, is seeking a Staff DFT Engineer to join their innovative team. This role is crucial in developing next-generation chiplet-based systems, focusing on power efficiency, area optimization, and manufacturing excellence. The position involves working with cutting-edge DFT (Design for Testability) methodologies, implementing scan and BIST features, and collaborating with cross-functional teams of industry experts.
The ideal candidate will have 6-9 years of experience in hardware engineering, with deep expertise in digital and analog/mixed-signal circuit design. You'll be responsible for defining DFT strategies, implementing RTL features, and ensuring comprehensive test coverage for high-speed interfaces. The role requires proficiency in Verilog/System Verilog and various industry-standard testing protocols (JTAG, IEEE1500, etc.).
This is an exciting opportunity to work in a fast-paced startup environment where innovation and first-principles thinking are valued. You'll be part of a team that's pushing the boundaries of chiplet technology, working on high-volume and high-performance products. The company offers excellent benefits and a fun work environment.
The position is based in the Bay Area and requires on-site presence. With the combination of technical challenges, professional growth opportunities, and the chance to work with industry experts, this role presents an excellent opportunity for experienced hardware engineers looking to make a significant impact in the semiconductor industry.
Responsibilities For Staff DFT Engineer
- Define DFT strategy, methodologies, and implementation plan
- Implement DFT features in RTL for digital and analog blocks
- Run ATPG and create and simulate DFT vectors
- Generate and insert TAP/JTAG interface for chiplet/IP designs
- Work with Analog/Mixed Signal (AMS) teams to ensure DFT coverage for high-speed interfaces
- Work with circuit architects on boundary scan and loopback capabilities
- Prepare vectors for post-silicon bring up (DVT vs. ATE)
- Report status of DFT test coverage and mitigation strategy to narrow down holes
Requirements For Staff DFT Engineer
- General knowledge of digital and AMS circuit design techniques
- Broad knowledge of DFT methodologies and tools
- Proficient in Verilog/System Verilog and scripting
- Ability to work collaboratively with cross functional team
- Prepare test vectors and collateral for ATE test team
- BS EE or equivalent, with 6-9 years of experience
- Breadth of expertise in MBIST, JTAG, IEEE1500, 1149, 1687, 1838
- 3+ experience with Siemens Tessent MBIST, Scan Insertion and SSN flow
- MS/PhD EE or equivalent preferred
Benefits For Staff DFT Engineer
- Excellent benefits
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