ASIC Design Verification Engineer, Machine Learning
Description For ASIC Design Verification Engineer, Machine Learning
Google is seeking an ASIC Design Verification Engineer to join their ML, Systems, & Cloud AI (MSCA) organization, focusing on shaping the future of AI/ML hardware acceleration. This role offers an exciting opportunity to work on cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications.
The position involves developing custom silicon solutions that power Google's TPU infrastructure, contributing to the innovation behind products used by millions worldwide. You'll leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As part of the team, you'll be responsible for developing ASICs used to accelerate computation in data centers, participating in project definition, design verification, and silicon bringup. The role involves collaborating with design engineers, creating verification environments using SystemVerilog and UVM, and ensuring thorough testing of design blocks.
The position offers competitive compensation ranging from $132,000 to $189,000, plus bonus, equity, and comprehensive benefits. You'll be part of Google's global impact spanning software and hardware, including Google Cloud's Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
This role requires strong technical expertise in ASIC design verification, with a minimum of 3 years of experience and a bachelor's degree in a relevant field. The ideal candidate will have experience with SystemVerilog, industry-standard simulators, and the full verification lifecycle. You'll work in Madison, WI, contributing to Google's mission of advancing AI/ML hardware capabilities while collaborating with world-class engineers and researchers.
Responsibilities For ASIC Design Verification Engineer, Machine Learning
- Plan the verification of digital design blocks, understand the design specification, and interact with design engineers to identify important verification scenarios
- Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM)
- Identify and write all types of coverage measures for stimulus and corner-cases
- Debug tests with design engineers to deliver correct design blocks
- Close coverage measures to identify verification holes and to show progress towards tape-out
Requirements For ASIC Design Verification Engineer, Machine Learning
- Bachelor's degree in Computer Science, Electrical Engineering, a related field, or equivalent practical experience
- 3 years of experience with industry standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips
- Experience with SystemVerilog (i.e., SystemVerilog Assertions or functional coverage)
Benefits For ASIC Design Verification Engineer, Machine Learning
- Medical Insurance
- Equity
- 401k
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