ASIC Engineer, IP Design
Description For ASIC Engineer, IP Design
Join Google's innovative hardware team as an ASIC Engineer focusing on IP Design, where you'll be instrumental in developing custom silicon solutions that power Google's direct-to-consumer products. This role involves designing foundation and chassis IPs for Pixel System on Chips (SoCs), including Network on Chip (NoC), Clock, Debug, IPC, and Memory Management Unit (MMU) components.
You'll work at the intersection of hardware and software, collaborating with cross-functional teams in architecture, software, verification, power, and timing to deliver high-quality Register-Transfer Level (RTL) designs. The position requires expertise in microarchitecture, low power design methodology, and the ability to evaluate design options considering performance, power, and area constraints.
As part of Google's mission to organize the world's information and make it universally accessible, you'll be contributing to a team that combines the best of Google AI, Software, and Hardware to create groundbreaking user experiences. The role offers the opportunity to work on projects that directly impact millions of users worldwide, pushing the boundaries of hardware innovation.
The ideal candidate brings strong technical expertise in RTL design, ARM-based SoCs, and ASIC methodology, along with programming skills in languages like Python or Perl. You'll be responsible for everything from defining microarchitecture details to performing RTL development and quality checks, making this an excellent opportunity for someone passionate about hardware design and innovation at scale.
Working at Google, you'll be part of a company committed to equal opportunity and creating a culture of belonging, with comprehensive benefits and the chance to work on cutting-edge technology that shapes the future of computing.
Responsibilities For ASIC Engineer, IP Design
- Work as part of the team that delivers coherent fabric interconnect solutions
- Define microarchitecture details such as interface protocol, block diagram, data flow, pipelines, etc
- Perform RTL development (SystemVerilog), debug functional/performance simulations
- Perform RTL quality checks including Lint, CDC, Synthesis, UPF checks
- Participate in synthesis, timing/power estimation, and FPGA/silicon bring-up
Requirements For ASIC Engineer, IP Design
- Bachelor's degree in Electrical or Computer Engineering or equivalent practical experience
- 5 years of experience with Register-Transfer Level (RTL) design using Verilog/System Verilog and microarchitecture
- 5 years of experience with ARM-based System on a Chip (SoCs), interconnects and Application-Specific Integrated Circuit (ASIC) methodology
- Experience with a coding language like Python or Perl
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