ASIC Engineer, IP Design, Silicon
Description For ASIC Engineer, IP Design, Silicon
Google is seeking an ASIC Engineer to join their Silicon team, focusing on IP Design. This role is crucial in developing custom silicon solutions that power Google's direct-to-consumer products. The position combines hardware engineering with software development, requiring expertise in RTL design, microarchitecture, and automation.
The ideal candidate will work on cutting-edge technology that impacts millions of users worldwide, contributing to Google's mission of organizing world information and making it universally accessible. The role involves working with state-of-the-art hardware development, including RTL development using SystemVerilog, quality checks, and FPGA/silicon bring-up.
As part of Google's hardware team, you'll collaborate with multi-disciplined teams across different locations, contributing to the innovation behind Google's hardware experiences. The position offers the opportunity to work on projects that deliver unparalleled performance, efficiency, and integration.
The role requires a strong background in electrical/computer engineering, with hands-on experience in RTL design and scripting languages. You'll be responsible for defining microarchitecture details, performing RTL development, and ensuring quality through various checks and validations. This position is perfect for someone who wants to combine hardware expertise with Google's innovative technology stack.
Responsibilities For ASIC Engineer, IP Design, Silicon
- Define microarchitecture details, block diagram, data flow, pipelines, etc.
- Perform RTL development (SystemVerilog), debug functional/performance simulations
- Perform RTL quality checks including Lint, CDC, Synthesis, UPF checks
- Participate in synthesis, timing/power estimation and FPGA/silicon bring-up
- Communicate and work with multi-disciplined and multi-site teams
Requirements For ASIC Engineer, IP Design, Silicon
- Bachelor's degree in Electrical/Computer Engineering or equivalent practical experience
- 3 years of experience with Register-Transfer Level (RTL) design and integration using Verilog/System Verilog, microarchitecture and automation
- Experience with RTL design using Verilog/System Verilog and microarchitecture
- Experience with a scripting language like Python or Perl
Benefits For ASIC Engineer, IP Design, Silicon
- Equal employment opportunity
- Accommodations for special needs
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