ASIC Power Management Architect, Silicon
Description For ASIC Power Management Architect, Silicon
Join Google's innovative hardware team as an ASIC Power Management Architect, where you'll be at the forefront of developing custom silicon solutions that power Google's direct-to-consumer products. This role combines advanced power management architecture with practical implementation, requiring expertise in both hardware and software aspects of system design.
You'll work on defining and implementing power management architectures for complex ASICs that include image compute and CPU/GPU functions, optimizing for maximum performance under power and thermal constraints. The position involves collaboration with software teams and power architecture specialists to create comprehensive system-level solutions.
Google's hardware team is dedicated to creating radically helpful experiences by combining the best of Google AI, Software, and Hardware. Your work will directly impact millions of users worldwide through next-generation hardware experiences that deliver unparalleled performance and efficiency.
This is an excellent opportunity for someone with strong technical expertise in power management systems and a passion for innovative hardware solutions. You'll be responsible for prototyping, validation, and detailed documentation of power management schemes, while also conducting trade-off analyses for engineering reviews and product roadmap decisions.
The role offers the chance to work with cutting-edge technology in a collaborative environment, contributing to products that push the boundaries of what's possible in consumer hardware. Your expertise in power management architecture will be crucial in developing sustainable, efficient, and high-performance solutions that align with Google's mission to organize the world's information and make it universally accessible and useful.
Responsibilities For ASIC Power Management Architect, Silicon
- Define ASIC power management architecture details for an ASIC that includes functions such as image compute, CPU/GPU
- Prototype and validate for the next generation SoC power management system
- Analyze implementation and models, and test the performance of power management solutions
- Produce detailed documentation for power management schemes implementation
- Collaborate with software and power architecture team to build system level designs and methods
Requirements For ASIC Power Management Architect, Silicon
- Bachelor's degree in Electrical Engineering or equivalent practical experience
- 5 years of experience in power management or post-silicon measurements and validation
- 3 years of experience with power management validation
- Knowledge of Dynamic Voltage Frequency Scaling (DVFS), idle power management, and system mitigation
- Knowledge of the impact of software and architectural design decisions on power and thermal behavior
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