ASIC Power Management Architect, Silicon

Join Google's innovative hardware team as an ASIC Power Management Architect, where you'll be at the forefront of developing custom silicon solutions that power Google's direct-to-consumer products. This role combines advanced power management expertise with architectural design to create next-generation hardware experiences.

As part of Google's mission to organize the world's information, you'll work at the intersection of AI, Software, and Hardware to create radically helpful experiences. The role involves defining power management architectures for ASICs, ensuring optimal performance while managing power and thermal constraints. You'll be responsible for algorithm development, modeling, and implementing sophisticated power management techniques.

The ideal candidate brings deep expertise in power components, ASIC design, and system-level power management. You'll work with cutting-edge technologies including Voltage Frequency Scaling, Power Management ICs, and power delivery networks. Your work will directly impact the efficiency and performance of Google's hardware products used by millions worldwide.

This position offers the opportunity to shape the future of Google's hardware architecture while working with world-class engineers and researchers. You'll be responsible for both technical implementation and strategic decision-making, producing detailed documentation and analysis that guides product roadmap decisions.

The role combines technical depth with strategic thinking, requiring both hands-on engineering skills and the ability to communicate complex technical concepts. Join a team that's pushing the boundaries of what's possible in hardware design and help create the next generation of Google's innovative products.