ASIC RTL Design Engineer

Google organizes the world's information and makes it universally accessible and useful, combining AI, Software, and Hardware to create helpful experiences.
Embedded
Entry-Level Software Engineer
In-Person
5,000+ Employees
Enterprise SaaS

Description For ASIC RTL Design Engineer

Google is seeking an ASIC RTL Design Engineer to join their hardware team that develops custom silicon solutions for Google's direct-to-consumer products. This role is part of Google's mission to organize the world's information and make it universally accessible and useful. The team combines Google AI, Software, and Hardware to create innovative experiences.

As an ASIC RTL Design Engineer, you'll be working on cutting-edge hardware development, contributing to products used by millions worldwide. The role involves RTL development using SystemVerilog, performing various quality checks, and working on synthesis and FPGA/silicon bring-up. You'll be part of a team that pushes boundaries in hardware innovation.

The ideal candidate should have a strong foundation in Electrical/Computer Engineering with experience in RTL design, scripting languages, and ARM-based SoCs. Additional expertise in IP design for clocking, interconnects, and peripherals would be valuable. This position offers the opportunity to shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Working at Google means joining a company committed to innovation and technical excellence, with a strong focus on creating radically helpful experiences through technology. You'll collaborate with multi-disciplined teams across different locations, contributing to projects that have global impact. The role offers exposure to advanced hardware development processes and the chance to work with cutting-edge technology in silicon design.

Last updated 33 minutes ago

Responsibilities For ASIC RTL Design Engineer

  • Perform RTL development (SystemVerilog), debug functional/performance simulations
  • Perform RTL quality checks including Lint, CDC, Synthesis, UPF checks
  • Participate in synthesis, timing/power estimation and FPGA/silicon bring-up
  • Communicate and work with multi-disciplined and multi-site teams

Requirements For ASIC RTL Design Engineer

Python
  • Bachelor's degree in Electrical/Computer Engineering
  • Experience with RTL design using Verilog/System Verilog and microarchitecture
  • Experience with a scripting language like Python or Perl
  • Experience with ARM-based SoCs, interconnects and ASIC methodology

Interested in this job?

Jobs Related To Google ASIC RTL Design Engineer

ASIC RTL Design Engineer

ASIC RTL Design Engineer position at Google, focusing on custom silicon development and hardware innovation for consumer products.

Application-Specific Integrated Circuit (ASIC) Design Verification Engineer

ASIC Design Verification Engineer position at Google, focusing on verifying digital systems and developing verification methodologies for custom silicon solutions.

ASIC Design Engineer Silicon

ASIC Design Engineer position at Google, focusing on custom silicon solutions and RTL development for next-generation hardware products.

CPU RTL Design Engineer, University Graduate

Entry-level CPU RTL Design Engineer position at Google, focusing on custom silicon solutions and next-generation processor design with competitive compensation and benefits.

CPU Frontend Design Engineer, Google Cloud, University Graduate

Entry-level CPU Frontend Design Engineer position at Google Cloud, focusing on CPU development and RTL design for server Systems on Chip, suitable for university graduates with hardware engineering background.