ASIC RTL Design Engineer
Description For ASIC RTL Design Engineer
Google is seeking an ASIC RTL Design Engineer to join their hardware team in Bengaluru. This role is part of Google's initiative to develop custom silicon solutions that power their direct-to-consumer products. The position combines hardware engineering with Google's expertise in AI and software to create innovative computing experiences.
As an ASIC RTL Design Engineer, you'll be working on cutting-edge hardware development, focusing on RTL design using SystemVerilog and microarchitecture. You'll be responsible for developing and debugging functional/performance simulations, performing various quality checks, and participating in the synthesis and timing/power estimation processes.
The ideal candidate should have a strong foundation in Electrical/Computer Engineering with hands-on experience in RTL design, ARM-based SoCs, and ASIC methodology. Knowledge of scripting languages like Python or Perl is essential for automation and tooling tasks.
This is an excellent opportunity for someone looking to work on hardware that impacts millions of users worldwide. You'll be part of a team that pushes boundaries in silicon development, working on projects that require both technical expertise and innovative thinking. The role offers the chance to work with multi-disciplined teams across different locations, contributing to Google's mission of organizing the world's information and making it universally accessible.
Responsibilities For ASIC RTL Design Engineer
- Perform RTL development (SystemVerilog), debug functional/performance simulations
- Perform RTL quality checks including Lint, CDC, Synthesis, UPF checks
- Participate in synthesis, timing/power estimation and FPGA/silicon bring-up
- Communicate and work with multi-disciplined and multi-site teams
Requirements For ASIC RTL Design Engineer
- Bachelor's degree in Electrical/Computer Engineering
- Experience with RTL design using Verilog/System Verilog and microarchitecture
- Experience with a scripting language like Python or Perl
- Experience with ARM-based SoCs, interconnects and ASIC methodology
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