Full Chip Physical Integration and CAD Engineer, Silicon
Description For Full Chip Physical Integration and CAD Engineer, Silicon
Join Google's innovative hardware team as a Full Chip Physical Integration and CAD Engineer, where you'll be at the forefront of developing custom silicon solutions that power Google's direct-to-consumer products. This role combines advanced ASIC physical design with mixed-signal expertise, requiring deep technical knowledge in RTL2GDS flows, timing analysis, and power optimization. You'll work on cutting-edge projects that directly impact millions of users worldwide, contributing to Google's mission of organizing the world's information and making it universally accessible.
As a senior technical member, you'll take ownership of physical design integration and CAD flow for mixed signal chip development, driving critical aspects of chip design from implementation to sign-off. The role demands expertise in synthesis, place and route (PnR), and sign-off convergence, including static timing analysis, power distribution network, and physical verification. You'll be responsible for developing and implementing innovative methodologies to optimize Performance, Power, and Area (PPA) metrics.
The position offers the opportunity to work with Google's best-in-class AI, Software, and Hardware teams, contributing to the next generation of hardware experiences. You'll be part of a team that pushes boundaries in advanced process nodes, developing solutions that deliver unparalleled performance, efficiency, and integration. This role is perfect for experienced professionals who want to make a significant impact on Google's hardware innovation while working with cutting-edge technology and world-class teams.
Responsibilities For Full Chip Physical Integration and CAD Engineer, Silicon
- Develop all aspects of RTL2GDS for ASIC/Mixed signal chips
- Complete ownership of physical design integration and CAD flow for Mixed signal chip development
- Drive the closure of timing and power/Physical convergence of the design
- Contribute to physical design methodologies and automation scripts for various implementation steps
- Define and implement innovative schemes to improve Performance, Power, Area (PPA) and CAD methodology
Requirements For Full Chip Physical Integration and CAD Engineer, Silicon
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 10 years of experience in ASIC physical design flows and methodologies in advanced process nodes
- Experience in synthesis, Place and route (PnR), sign-off convergence including Static timing analysis (STA), PDN, electrical checks, and physical verification
- Experience in analog mixed signal design/CAD automation/Physical integration
- Experience with mixed-signal design
Jobs Related To Google Full Chip Physical Integration and CAD Engineer, Silicon
