Lead CPU Performance Architect, Silicon

Google is seeking a Lead CPU Performance Architect to join their Silicon team, working on custom silicon solutions that power Google's direct-to-consumer products. This is a senior-level position requiring extensive experience in CPU architecture and performance optimization.

The role involves leading CPU architecture and performance initiatives, developing innovative micro-architecture features, and delivering advanced SoC products. You'll work closely with Google's Android applications and Artificial Intelligence teams to conduct performance analysis and projections throughout various design phases.

Key responsibilities include delivering solutions for CPU performance, micro-architecture design, and methodology, as well as leading collaboration with RTL, design verification, and physical design teams. The position requires expertise in processor instruction set architecture (ARM, RISC-V, x86) and system software components.

The ideal candidate will have at least 8 years of experience in high-performance microprocessor architecture and a Master's degree in a relevant field. Strong technical skills combined with excellent communication abilities are essential, as you'll be working across multiple teams and driving critical architecture decisions.

This is an excellent opportunity for an experienced CPU architect looking to make an impact at scale, working on products used by millions worldwide. Google offers competitive compensation including base salary, bonus, equity, and comprehensive benefits. The role provides the chance to work with cutting-edge technology and shape the future of Google's hardware experiences.

The position is available in multiple locations including Austin, Mountain View, Portland, and Poughkeepsie, offering flexibility in work location while maintaining an in-person work environment. You'll be part of Google's commitment to innovation and excellence in silicon development, working on projects that push the boundaries of what's possible in consumer technology.