Network Register Transfer Level Design Engineer, Google Cloud
Description For Network Register Transfer Level Design Engineer, Google Cloud
Join Google's ML, Systems, & Cloud AI (MSCA) organization as a Network Register Transfer Level Design Engineer, where you'll be instrumental in developing custom silicon solutions that power Google's data center infrastructure. This role combines hardware expertise with networking knowledge, focusing on developing Application-Specific Integrated Circuits (ASICs) to accelerate networking in data centers. You'll be responsible for everything from project definition to implementation, working on next-generation data center accelerators and performing performance analysis for end-to-end networking stacks. The position requires deep knowledge of RDMA-based transports and involves collaboration with cross-functional teams to develop cutting-edge networking solutions. This is an opportunity to impact Google's global infrastructure, working on projects that affect billions of users worldwide through Google's services and Cloud platform. The role offers the chance to work with state-of-the-art technology while contributing to the future of hyperscale computing and data center networking.
Responsibilities For Network Register Transfer Level Design Engineer, Google Cloud
- Participate in evaluation of future ASIC designs and general architecture for executing Google's data center networking roadmap
- Collaborate to develop new layer protocols for data center networking
- Understand how everything interacts with software and other ASIC subsystems to implement data center networks
- Define performance hardware/software interfaces. Write micro-architecture and design specifications
- Define efficient micro-architecture and block partitioning/interfaces and flows
Requirements For Network Register Transfer Level Design Engineer, Google Cloud
- Bachelor's degree or equivalent practical experience
- 8 years of experience architecting networking ASICs from specification to production
- Experience working with design networking like: RDMA and or packet processing and system design principles
- Experience developing Register Transfer Level (RTL) for ASIC subsystems
- Experience in Cross-functional, micro-architecture, design, verification, logic synthesis, and timing closure
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